MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 87

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

5.8.3 SCI Status Register
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
Register name and address: SCI Status Register (SCSRA), $XXXX1C
Reset:
Read:
Write:
Bit 15
0
= Unimplemented
14
0
Figure 5-12. SCI Status Registers (SCSRA and SCSRB)
13
0
SCI Status Register (SCSRB), $XXXX2C
The SCSR contains flags that show SCI operating conditions. These
flags are cleared either by SCI hardware or by a read/write sequence.
To clear SCI transmitter flags, read the SCSR and then write to the
SCDR. To clear SCI receiver flags, read the SCSR and then read the
SCDR. A long-word read can consecutively access both the SCSR and
the SCDR. This action clears receiver status flag bits that were set at the
time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has
read the asserted status bits, but before the CPU has written or read the
SCDR, the newly set status bit is not cleared. The SCSR must be read
again with the bit set, and the SCDR must be written to or read before
the status bit is cleared.
Reading either byte of the SCSR causes all 16 bits to be accessed, and
any status bit already set in either byte will be cleared on a subsequent
read or write of the SCDR.
Bits 15–9 — Not implemented
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
12
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0
For More Information On This Product,
0 = The TDR still contains data to be sent to the transmit serial
1 = A new character may now be written to register TDR.
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
11
0
shifter.
Go to: www.freescale.com
10
0
SCI Submodule
0
9
TDRE
8
1
TC
7
1
RDRF RAF IDLE
0
6
5
0
0
4
OR
3
0
Reference Manual
NF
0
2
SCI Submodule
SCI Registers
FE
1
0
Bit 0
PF
0
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