MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 52

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

SPI Submodule
4.12.1 SPI Control Register
Register address: $XXXX38
Reference Manual
52
Reset:
Read:
Write:
Bit 15
SPIE
0
SPE WOMP MSTR CPOL CPHA LSBF SIZE
14
0
13
0
The SPI control register (SPCR) contains parameters for configuring the
SPI. The register can be read or written at any time.
SPIE — SPI Interrupt Enable Bit
SPE — SPI Enable Bit
WOMP — Wired-OR Mode for SPI Pins
MSTR — Master/Slave Mode Select Bit
CPOL — Clock Polarity Bit
12
0
Figure 4-4. SPI Control Register (SPCR)
To prevent unpredicted operation, the other SPI control fields should
be configured properly before or at the same time SPE is set.
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0 = SPI interrupts disabled
1 = SPI interrupts enabled
0 = SPI disabled
1 = SPI enabled
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by MDDR have open-drain drivers,
0 = SPI is a slave device.
1 = SPI is system master.
0 = The inactive state value of SCK is logic level 0.
1 = The inactive state value of SCK is logic level 1.
11
0
regardless if the pins are used as SPI outputs or for
general-purpose I/O, and regardless if the SPI is enabled.
10
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1
SPI Submodule
9
0
8
0
0
7
Multichannel Communication Interface — Rev. 1.0
6
0
5
0
4
0
BAUD
3
0
2
1
MOTOROLA
1
0
Bit 0
0