MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 47

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

4.6.2 CPHA = 1 Transfer Format
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
FOR REFERENCE
SCK (CPOL = 0)
SCK (CPOL = 1)
FROM MASTER
SCK CYCLE #
FROM SLAVE
SS TO SLAVE
MOSI
MISO
Not defined, but normally LSB of previously transmitted character.
For a master, writing to the SPDR initiates the transfer. For a slave, the
falling edge of SS indicates the start of a transfer. The SCK signal
remains inactive for the first half of the first SCK cycle. Data is latched
on the first and each succeeding odd clock edge, and the SPI shift
register is left-shifted on the second and succeeding even clock edges.
SPIF is set at the end of the eighth SCK cycle.
When CPHA equals 0, the SS line must be negated and reasserted
between each successive serial byte. If the slave writes data to the SPI
data register while SS is asserted (low), a write collision error results. To
avoid this problem, the slave should read bit 3 of PORTMCP, which
indicates the state of the SS pin, before writing to the SPDR again.
Figure 4-3
CPHA equals 1. Two waveforms are shown for SCK, one for CPOL
equal to 0 and another for CPOL equal to 1. The diagram may be
interpreted as a master or slave timing diagram since the SCK, MISO,
and MOSI pins are directly connected between the master and the slave.
The MISO signal shown is the output from the slave and the MOSI signal
shown is the output from the master. The SS line is the slave select input
to the slave.
Figure 4-3. CPHA = 1 SPI Transfer Format
Freescale Semiconductor, Inc.
MSB
MSB
1
For More Information On This Product,
2
is a timing diagram of an 8-bit, MSB-first SPI transfer in which
6
6
Go to: www.freescale.com
SPI Submodule
3
5
5
4
4
4
5
3
3
6
2
2
SPI Clock Phase and Polarity Controls
7
1
1
LSB
8
LSB
Reference Manual
SPI Submodule
47