MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 77

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MCCIRM

Manufacturer Part Number
MCCIRM
Description
MCCIRM Multi-Channel Communications Interface Reference Manual
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
5.7.11 Frame Detection and Synchronization
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
When the MSB of a frame is set, the receiver clears RWU and wakes up.
The byte is received normally and is transferred to the RDR, and the
RDRF flag is set. If software does not recognize the address, it can set
RWU and put the receiver back to sleep. Address-mark wakeup allows
idle time between frames and eliminates idle time between
transmissions. However, there is a loss of efficiency due to an additional
bit time per frame.
After RE is set, bit processor logic begins to sample the signal on the
RXD pin. The sampling process identifies a valid start bit and
synchronizes the receiver with the incoming frame. A receive time (RT)
clock is used to control sampling and synchronization. Data is shifted
into the receive serial shifter according to the most recent
synchronization of the RT clock with the incoming data stream. From this
point on, the data movement is synchronized with the MCU system
clock. Understanding this process can be useful in determining the
amount of baud-rate frequency mismatch that can be tolerated. It also
indicates how well this SCI receiver can handle noise.
RT clock rate is 16 times the baud clock rate. Each bit time of a received
frame is divided into 16 sample periods designated RT1–RT16.
Designations are assigned relative to the time a start bit is detected. The
receiver active flag (RAF) in SCSR is set when a valid start bit is
identified.
Synchronicity is maintained throughout the frame. Sampling continues
and the receiver resynchronizes on each 1-to-0 transition in the frame.
Bit time normally begins at RT1 and ends at RT16. After the frame ends,
the receiver begins the process of identifying the next start bit.
Synchronization at the beginning of each incoming frame eliminates
cumulative timing errors due to small differences between the baud rates
of the receiver and the transmitter. Synchronization on each 1-to-0
transition in the frame increases tolerance to small frequency variations
in the received data stream.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
SCI Submodule
Reference Manual
SCI Submodule
SCI Transmitter
77

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