MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 78

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

SCI Submodule
5.7.11.1 Start Bit Detection
5.7.11.2 Logic Level Detection
Reference Manual
78
When the receiver is first enabled or when a stop bit is received at the
end of a frame, an asynchronous search is initiated to find the leading
edge of the next start bit. The goal of this asynchronous search is to gain
bit-time synchronization between the serial data stream and the internal
RT clock. Once synchronization has been established, the RT clock
controls where the MCU perceives the bit-time boundaries to be.
The first step in locating a start bit is to find a sample where RXD is 0
preceded by three consecutive samples of logic 1. These four samples
are called start-bit qualifiers. Until the start-bit qualifiers are detected, the
RT clock is reset to state RT1 after each sample. Once the qualifiers are
found, the beginning of a start bit is tentatively assumed, and
subsequent samples are assigned successive RT state numbers. Next,
start-bit verification samples are taken at RT3, RT5, and RT7. If any two
of the three verification samples are logic 1s, the low at the start-bit
qualifiers and the start-bit verification requirements are met,
synchronization has been achieved, and the RT count state is used to
determine the position of bit-time boundaries.
Data samples are taken at RT8, RT9, and RT10 of each bit time,
including start and stop bit times, to determine the logic level of the bit
time and to set a working noise flag, if necessary. The logic level of the
bit time is considered to be the majority of all samples taken during bit
time. Even if the samples at RT8, RT9, and RT10 suggest it should be
1, however, the logic level of the start bit is always assumed to be 0.
If there is any disagreement among the samples taken during any bit
time in a frame (including the start and stop bit times), the internal noise
flag is set. At the end of a character reception, data is transferred from
the receive shifter to the parallel RDR, and the RDRF flag is set. If noise
was detected during reception of the character, the NF bit in the SCSR
is set at the same time as RDRF.
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SCI Submodule
Multichannel Communication Interface — Rev. 1.0
MOTOROLA