MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 27

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

3.5 Module Configuration
3.5.1 Low-Power Stop Mode
3.5.2 Privilege Levels
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
The MMCR contains bits and fields to:
When the STOP bit in the MMCR is set, the IMB clock signal to most of
the MCCI module is disabled. This places the module in an idle state and
minimizes power consumption.
To ensure that the MCCI stops in a known state, assert the STOP bit
before executing the CPU LPSTOP instruction. Before asserting the
STOP bit, disable the SPI (clear the SPE bit), and disable the SCI
receivers and transmitters (clear the RE and TE bits). Complete
transfers in progress before disabling the SPI and SCI interfaces.
Once the STOP bit is asserted, it can be cleared by system software or
by reset.
In systems that support privilege levels, the CPU can operate at either
of two levels of access: user or supervisor. MCCI global registers
(MMCR, MTEST, ILSCI, MIVR, and ILSPI) can be accessed only when
the CPU is operating at the supervisor level. The supervisor bit (SUPV)
in the MMCR determines whether the CPU can access the remaining
MCCI registers from the supervisor level only or from either privilege
level. In systems that do not support privilege levels, the CPU always
operates at the supervisor level.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Place the MCCI in low-power operation
Establish the privilege level required to access MCCI registers
Establish the priority of the MCCI during interrupt arbitration
Go to: www.freescale.com
Configuration and Control
Configuration and Control
Module Configuration
Reference Manual
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