MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 50

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

SPI Submodule
4.11 Mode Fault
Reference Manual
50
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. Since a master is in control of the
transfer, software can avoid a write collision error generated by the
master. The SPI logic can, however, detect a write collision in a master
as well as in a slave.
What constitutes a transfer in progress depends on the SPI
configuration. For a master, a transfer starts when data is written to the
SPDR and ends when SPIF is set. For a slave, the beginning and ending
points of a transfer depend on the value of CPHA. When CPHA = 0, the
transfer begins when SS is asserted and ends when it is negated. When
CPHA = 1, a transfer begins at the edge of the first SCK cycle and ends
when SPIF is set. Refer to
for more information on transfer periods and on avoiding write collision
errors.
When a write collision occurs, the WCOL bit in the SPSR is set. To clear
WCOL, read the SPSR while WCOL is set, and then either read the
SPDR (either before or after SPIF is set) or write the SPDR after SPIF is
set. (Writing the SPDR before SPIF is set results in a second write
collision error.) This process clears SPIF as well as WCOL.
When the SPI system is configured as a master and SS input line is
asserted, a mode fault error occurs, and the MODF bit in the SPSR is
set. Only an SPI master can experience a mode fault error, caused when
a second SPI device becomes a master and selects this device as if it
were a slave. To avoid latchup caused by contention between two pin
drivers, the MCU does the following when it detects a mode fault error:
1. Forces the MSTR control bit to 0 to reconfigure the SPI as a slave
2. Forces the SPE control bit to 0 to disable the SPI system
3. Sets the MODF status flag and generates an SPI interrupt if
4. Clears the appropriate bits in the MDDR to configure all SPI pins
Freescale Semiconductor, Inc.
For More Information On This Product,
SPIE = 1
except the SS pin as inputs
Go to: www.freescale.com
SPI Submodule
4.6 SPI Clock Phase and Polarity Controls
Multichannel Communication Interface — Rev. 1.0
MOTOROLA