cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 104

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.5.2
Figure 2-21. Far-End Line Loopback Diagram
2-66
LRxSync
LRxData
LTxSync
Interface
LTxData
LRxClk
LTxClk
Framer
(Line)
This segment is replicated for Ports 0–11
Loopback
Control
Far-End Line Loopback
When the Far-End Line Loopback control bit is set, PMODE[FELNLOOP], a
UTOPIA loopback is enabled. Received cells are processed normally up to the
UTOPIA block but are sent to the UTOPIA transmit block rather than output. Cells
from the UTOPIA transmit bus are ignored.
NOTE:
TCK
Preliminary Information/Mindspeed Proprietary and Confidential
TRST~
JTAG Controller
Transmitter
Receiver
Line
Line
TMS
TDI
Mindspeed Technologies™
When configuring the device for CD far-end loopback, continuous Start of Cell (SOC)
errors occur. These errors are incorrect because the UTOPIA interface is not being
used. The SOC interrupts must be disabled during the CD far-end loopback. Clear
EnSOCErrInt, bit 6, in the ENCELLT control register in the Cell Delineator group.
TDO
Alignment
Status and Control
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
8kHzIn
One Second Interface
OneSecIn
Microprocessor
Interface
4-cell
FIFO
4-cell
FIFO
OneSecOut
Interface
Interface
Transmit
UTOPIA
UTOPIA
Receive
Level 2
Level 2
Host
Host
CX28365/6/4 Data Sheet
UTOPIA
Level 2
Interface
UTxClk
UTxClav
UTxEnb~
UTxSOC
UTxData[15:0]
UTxPrty
UTxAddr[4:0]
URxClk
URxClav
URxEnb~
URxSOC
URxData[15:0]
URxPrty
URxAddr[4:0]
500028C
500028_038