cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 60

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.1.1.6
2-22
immediately starts if the FIFO buffer is not empty. If the last transmitted octet was an
EOM, FLAG sequences continue to be generated and transmitted.
From the system point of view, there are two TDL modes: Interrupt Driven mode and
Polling mode.
Interrupt Driven Mode
Unmasking at least one FIFO-related interrupt (Near-Empty, Underrun, or Message
Transmitted) enables interrupt driven mode.
Once an interrupt occurs, the microprocessor reads the Source Channel Status register
to identify which framer is the interrupt’s originator, then read the framer’s Interrupt
Source (i) Status register to identify which block raised the interrupt at the particular
framer (TDL in this case—bit TxDLFEACItr is high). It then reads the Transmit Data
Link FEAC Status register to identify the type of interrupt (Underrun, Near-Empty, or
Message Transmitted).
There are many available settings and methods of handling interrupts. The proposed
handling for normal operation is to read the Transmit Data Link FEAC Status register
as the interrupt occurs. If the TDL Near-Empty indication is set, a new block of data
bytes are written and transmitted (maximum 128 Near-Empty threshold bytes to
safely fill the FIFO buffer). After servicing this interrupt, the system waits for another
interrupt.
Polling Mode
Polling mode is effective when TDL function interrupts are masked. In Polling mode,
the service routine is executed based on timers. Here, after writing a message byte or a
message block of several bytes, the service routine waits for N milliseconds (based on
the data link rate and the block size written) and polls or samples the Transmit Data
Link FEAC Status register to check whether the FIFO buffer is empty or near empty,
and if so, writes another block. In this mode, TDL status is read before writing to the
FIFO buffer.
FIFO Special Events
End of Message Event
The system indicates End of Message (EOM) by writing the last byte of the message
to the high address of the Transmit Data Link Message Byte register. When the TDL
circuitry encounters the EOM indication set for a byte in the FIFO buffer, and after
transmitting the last byte, it checks whether FCS sequence sending is set (bit
TxFCSEn is set to 1 in Transmit Data Link Control register). If set, FCS bytes are
sent, followed by at least two FLAG sequences before starting transition of the next
message in the FIFO buffer (if there is one).
If the EOM byte is the last byte in the FIFO buffer, the TDL circuitry continues
transmitting FLAG sequences (after transmitting the last byte and FCS, if enabled)
until a new message byte is written to the FIFO buffer.
Near-Empty Event
The Near-Empty event is declared when the number of bytes remaining in the TDL
FIFO buffer is less than or equal to the number programmed at the Near-Empty
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
CX28365/6/4 Data Sheet
500028C