cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 43

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Figure 2-4. DS3 System Transmit Timing (TxSYNC Indicates Frame Start)
500028C
TxGCKO(inv)
TxGCKO
TxSYNC
TxDATI
TxCKI
Subframe 6
84 Payload bits
TxOvhMrk = 0, TxSync[i] is used for frame start indication. A transition from low to
high occurs between the last sampling edge of frame N and the first sampling edge of
frame N+1.
TxOvhMrk = 1, TxSync[i] is used for overhead bit indication including justification
control bits and stuff opportunity bits. TxSync[i] samples low at the corresponding
overhead bit with the sampling edge of TXCKI and samples high during all payload
bits.
If TxSync[i] is not used but selected via the INPORT2 Control registers, set the pin to
the output mode, TXSYOut = 1 and TXSYIn = 0.
Figure 2-4
signal. Also, payload bits only are inserted.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
illustrates the behavior of TxSYNC as a frame start synchronization output
Mindspeed Technologies™
The state TXSYOut = 1 and TXSYIn = 1 is not allowed.
M3
The full behavior is not
679 bits of Subframe 7 including its
shown for this section
Low during rest of Subframe 7
Subframe 7
overhead bits
X1
Subframe 1
84 Payload bits
Functional Description
500028_018
2
-
5