cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 58

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2-20
the last byte of the message. The writing to the high address marks the written byte as
the end of message byte (EOM). The next byte written to the FIFO buffer belongs to a
new message.
TDL FIFO Buffer Related Interrupts
All TDL FIFO interrupts are maskable individually. Settings in the Transmit Data
Link Control register control the enabling and disabling of the interrupts.
The TDL FIFO provides the following three interrupts:
TDL FIFO Related Status Bits
The TDL FIFO status indications are available at the Transmit Data Link FEAC Status
register to be read by the microprocessor. They are as follows:
Initial Setup of Transmit Data Link
The TDL is disabled on reset, with no interrupts active. Bits DLMod [2:0] in the
Transmit Overhead Insertion 1 Control register control TDL enabling for each mode.
1.
2.
3.
Preliminary Information/Mindspeed Proprietary and Confidential
TDL FIFO Near-Empty—(set and cleared with the interrupt) (indicated by the
TxNE bit)
TDL FIFO Empty—Indicates that the FIFO buffer is empty and has no message
bytes written to it (indicated by the TxEmpty bit).
TDL FIFO Underrun—(set and cleared with interrupt) (indicated by the TxUR
bit)
TDL Message Transmitted—(set and cleared with interrupt). Indicates that a full
message was transmitted including its closing FLAG (indicated by the TxMsg bit).
TDL FIFO Full—An indication bit that is set and stays set as long as the FIFO
buffer is full—128 bytes are stored inside the FIFO buffer. The FIFO Full status
can be used in polling mode to check if the FIFO buffer is full and there is no point
in writing to it (indicated by the TxFull bit).
TDL FIFO Near-Empty—(interrupt enabled by setting the TxNEIE bit to 1)
TDL FIFO Underrun—(interrupt enabled by setting the TxURIE bit to 1)
TDL Message Transmitted —(interrupt enabled by setting the TxMsgIE bit to 1)
Turned on when the number of data bytes that remains to be transmitted in the
Turned off when the TxMsg status bit at the Transmit Data Link FEAC Status
FIFO buffer becomes equal to or falls below the programmable Near-Empty
threshold level and the Near-Empty indication is not set.
Turned off when the number of data bytes that remained to be transmitted in
the FIFO buffer becomes higher than the programmable Near-Empty
threshold level.
The range of Near-Empty threshold settings is 0 to 126, and is set in the
TxNEThr[6:0] bit at the Transmit Data Link Threshold Control register.
Setting Near-Empty threshold to NE = 0 to 126, means that Near-Empty event
is declared when the number of data bytes remaining in the FIFO buffer is
equal or less than NE.
Turned on when the FIFO buffer is empty, if the last message byte that was
transmitted did not indicate an end of message byte, and the inner HDLC
circuitry requests the FIFO buffer for another byte to transmit.
Turned off when the Transmit Data Link FEAC Status register is read.
Turned on when the last bit of the closing FLAG of a message is transmitted.
register is read.
Mindspeed Technologies™
CX28365/6/4 Data Sheet
500028C