cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 99

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.4.3
2.4.4
500028C
Counters
One-Second Latching
There are counters in the cell delineator block that record events within the cell
delineator. Two types of events are recorded: error events, such as section BIP. errors,
and transmission events, such as transmitted ATM cells.
Counters comprised of more than one register must be accessed by reading the least
significant byte (LSB) first. This guarantees that the value contained in each
component register accurately reflects the composite counter value at the time the
LSB was read, because the counter may be updated while the component registers are
being read.
Each counter is large enough to accommodate the maximum number of events that
may occur within a one-second interval. The counters are cleared after being read.
Therefore, if the counters are read every second, the application will receive an
accurate recording of all events.
The CX2836x’s implementation of one-second latching ensures the integrity of the
statistics being gathered by network management software. Internal statistics counters
can be latched at one-second intervals, which are synchronized to the OneSecIn pin.
Therefore, the data read from the statistics counters represents the same one second of
real-time data, independent of network management software timing.
The CX2836x implements one-second latching for both status signals and counter
values. When the GLOB[EnStatLat] bit is written to a logical 1, a read from any status
register returns the state of the device at the time of the previous OneSecIn pin
assertion. When the GLOB[EnCntrLat] bit is written to a logical 1, a read from any
counter returns the state of the device at the time of the previous OneSecIn pin
assertion. Every second, the counter is read, moved to the latch, and the counter is
cleared. The latch is cleared when read.
OneSecIn is intended to be asserted at one-second intervals. This can be achieved by
connecting the OneSecIn pin to the OneSecOut pin. The OneSecOut signal is derived
from the 8kHzIn pin. This signal is asserted for one 8kHzIn period, every 8,000
8kHzIn periods. If 8kHzIn is being driven by an 8 kHz clock, the OneSecOut signal is
asserted every second.
NOTE:
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When latching is disabled and a counter is wider than one byte, the LSB should be
read first to retain the values of the other bytes for a subsequent read.
Functional Description
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