cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 93

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.3
2.3.1
500028C
UTOPIA Interface
UTOPIA Transmit and Receive FIFOs
The CX2836x uses the ATM Forum’s UTOPIA interface as its host interface to
communicate with the ATM layer device. This interface is UTOPIA Level 2-
compliant and UTOPIA Level 1-compatible. In brief, these two specifications are
described as follows:
The CX2836x’s UTOPIA block has two sections, transmit and receive, each of which
has a 4-cell FIFO buffer. ATM cell data is placed in the transmit FIFO buffers where it
can then be passed to the ATM cell processing block. On the receive side of the
UTOPIA interface, incoming cells are placed in the receive FIFO buffer until sent.
1.
2.
NOTE:
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
UTOPIA Level 1: This is an 8- or 16-bit interface designed for data rates up to
200 Mbps. Both octet-level and cell-level handshaking are supported at a clock
rate of 25 MHz. Octet-level handshaking requires the PHY to guarantee the
acceptance of at least 4 bytes before it asserts the TxFull control line. In cell-
level, it must guarantee the transfer of at least one entire 53-byte cell.
UTOPIA Level 2: This interface provides all the features of Level 1, plus several
enhancements. Level 2 defines multi-PHY functionality, allowing up to 31 PHYs
to interface to one ATM layer device. This interface uses either 8-bit or 16-bit
wide data buses and cell-level handshaking. The 16-bit mode, which can run at 50
MHz, supports data rates up to 800 Mbps.
Mindspeed Technologies™
PHY refers to a physical layer ATM port. Consequently, the CX2836x is a 12-PHY
device.
By convention, data being transferred from the PHY to the ATM layer is labeled
received data, while data from the ATM layer to the PHY is called transmitted data.
Functional Description
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