cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 49

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
500028C
The C-bits in M13/M23 modes are used as Justification Control bits and are all
supplied from the same source. Their options are as follows:
C-Bit Parity Mode Only: Overhead Insertion
In the C-bit parity mode of operation, the C-bits are divided into groups with the
following source options:
Preliminary Information/Mindspeed Proprietary and Confidential
X-bits (RAI)—Can be either inserted through the TEXTI pin (controlled by bit
ExtRAI in the Transmit Overhead Insertion 2 register) or can be generated by an
internal register setting (controlled by TxAlm[1:0] bits). When TxAlm[1:0] is set
to 01, bits X1 and X2 contain 0s regardless of other X-bits sourcing settings.
P-bits (parity bits)—Can be either internally calculated or inserted from TEXTI
pin (controlled by bit ExtP in the Transmit Overhead Insertion 2 register). When
set to be calculated internally, the transmitter calculates the parity over 4704
payload bits of each M-frame (even parity calculation is used) and inserts the
result into both P1 and P2 bits of the following M-frame.
Either to be inserted with the data stream (with or without the rest of the Overhead
bits) by setting ExtDat bit to 1 or ExtFEBE/Cj-bit to 0.
To be inserted through the TEXTI external pin. This option is chosen by setting
ExtDat bit to 0 and ExtFEBE/Cj-bit to 1.
AIC (Cb11)—Application Identification Channel. It is generated internally. The
transmitter inserts 1 to the transmitted data at the C11 place to indicate that the line
works with the C-bit parity application (a constant 1 at AIC-bit indicates C-bit
parity application).
FEAC (Cb13)—Far End Alarm Channel. When bit ExtFEAC/PD (Transmit
Overhead Insertion 1 Control register) is set to 1, Cb13 value is inserted through
the TEXTI input pin. When bit ExtFEAC/PD is set to 0, Cb13 is internally
generated using the Transmit FEAC Channel Byte register and setting bit
FEACSin (single or repetitive mode bit) at the Feature3 Control register.
Path Parity (Cb3)—The three C-bits at subframe 3 can either be supplied to the
transmitter circuit on TEXTI external input by setting bit ExtCP/TR in Transmit
Overhead Insertion 1 Control register to 1, or internally generated by setting bit
ExtCP/TR to 0. When internally generated, the transmitter calculates the parity
over 4704 payload bits of each M-frame (even parity calculation is used) and
inserts the result to Cb31, Cb32, and Cb33 bits of the next M-frame (they are all
set to the same value as the P-bits when no error insertion occurs).
FEBE (Cb4)—The three C-bits at subframe 4 (FEBE bits) can either be inserted
through the TEXTI pin (when ExtFEBE/Cj-bit in the Transmit Overhead Insertion
1 Control register is set to 1), or can have an internal-automatic source (when
ExtFEBE/Cj-bit is set to 0). The internal-auto sourcing of FEBE in DS3-C-bit
parity mode is further described in
DL (Cb5)—The three C-bits in subframe 5 are assigned as a 28.2 Kb terminal-to-
terminal path maintenance data link. Their values can be taken from the TEXTI
input pin when bits DLMod[2] and DLMod[1] are set to 11. The bits can all be
automatically set to 1 by setting bit DLMod[2] to 0 (DLMod[1] bit can be set to
either 0/1), or they can be chosen internally by registers generated by setting
DLMod[2] and DLMod[1] bits to 10. The last option uses an internal FIFO buffer
and the HDLC formatting mechanism to implement LAPD data link channel on
those bits. For details, see
Cb12, Cb2, and Cb6–7—Cb12 is an NR bit (network reserved bit). The C-bits in
Mindspeed Technologies™
Section
2.1.1.6.
Section
2.1.1.4.
Functional Description
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