cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 69

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Figure 2-14. Receiver System Side Outputs [REXTCKO]
Figure 2-15. Receiver System Side Outputs
500028C
b)
d)
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a)
a)
e)
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2.
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and overhead marker signal.
Options are available (via the RxAll1 and RxAIS fields of the CR08 register) to
produce either an all 1s or an AIS output, respectively, on the RxDATO pin,
completely masking the received input. In addition, automatic assertion of an all 1s
stream is available (via the RxAutoAll1 mode control bit in CR08 register). In this
case, detection of one or more of the following events produces an all 1-s sequence:
LOS, OOF, AIS, Idle in DS3 mode, and LOS, OOF, AIS in E3 mode.
Termination of these events, terminates the all-1s stream assertion. The received data
is otherwise normally handled and results in all expected indications and performance
monitoring.
P
P
Figure 2-15
Preliminary Information/Mindspeed Proprietary and Confidential
C
C
P
P
Mindspeed Technologies™
O
O
illustrates two options of RxSync signal, frame synchronization signal,
P
P
O
O
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P
RxCKI, receive clock
RxDATO, data output
REXTCKO, no output
REXTCKO, partial overhead bit
output, rising edge polarity (non-inverted)
REXTCKO, partial overhead bit
output, falling edge polarity (inverted)
REXTCKO, full payload and overhead
bit output
RxCKI, receive clock
RxDATO, data output
RxSync, frame synchronization option
RxSync, overhead marker option
Functional Description
500028_027
500028_028
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