cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 174

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x42—SR02 (Counter Interrupt Status Register)
EXZCtrltr
XDgrCtrltr
LCVCtrltr
FEBECtrltr
PthCtrltr
FerrCtrltr
PdgrCtrltr
ParCtrltr
3-64
EXZCtrltr
7
XDgrCtrltr
Excessive Zeros Counter Interrupt—Set high on EXZ error counter rollover or saturation. The
EXZ Counter Interrupt Enable bit, EXZCtrlE bit in Counter Interrupt Control register,
determines the status of the counter (rollover or saturation).
X-Bits Disagreement Counter Interrupt—Set high if the X-Disagreement counter has either
rolled over or is saturated. The X-Disagreement Counter Interrupt Enable bit (XDgrCtrIE)
determines the status of the counter (rollover or saturation). In E3-G.751 and E3-G.832 modes,
this bit is low because there are no X-bits.
LCV Counter Interrupt—Set high on an LCV error counter rollover or saturation. The LCV
Counter Interrupt Enable bit (LCVCtrIE) determines the status of the counter (rollover or
saturation).
FEBE Event Counter Interrupt—Set high if the FEBE event counter has either rolled over or is
saturated. The FEBE Event Counter Interrupt Enable bit determines the status of the counter
(rollover or saturation).
In E3-G.751 and DS3-M13/M23 modes, this bit is low because there is no FEBE/REI event
defined.
Path Parity Error Counter Interrupt—In DS3 mode, set high if the Path Parity Error counter
has either rolled over or is saturated. The Path Parity Error Counter Interrupt Enable bit
determines the status of the counter (rollover or saturation).
In DS3-M13/M23, E3-G.751, and E3-G.832 modes, this bit is low because there is no path
parity check.
Frame Error Counter Interrupt—Set high when the frame error counter has either rolled over
or is saturated. The Frame Error Counter Interrupt Enable determines the status of the counter
(rollover or saturation).
P-Bits Disagreement Counter Interrupt—Set high if the P disagreement counter has either
rolled over or is saturated. The Disagreement Counter Interrupt Enable bit determines the
status of the counter (rollover or saturation). In E3-G.751 and E3-G832 modes, this bit is low
because there is no parity disagreement event defined.
Parity Error Counter Interrupt—Set high if the parity error counter has either rolled over or is
saturated. The Parity Error Counter Interrupt Enable bit determines the status of the counter
(rollover or saturation). In E3-G.751 mode, this bit is low because there is no parity/BIP-8
check defined.
6
The Counter Interrupt Status register contains status information about active
interrupts needing service from the controller. This register must be read by the
controller upon receiving a counter interrupt to determine the source of the interrupt.
The interrupt indications are active high in the register and are available even if they
are not enabled to be visible on the MINTR* output pin. Servicing clears this interrupt
indication.
The bits in this register are cleared when the register is read.
Value after reset: 00
Direction: Read only
Value after enable: 00
Preliminary Information/Mindspeed Proprietary and Confidential
LCVCtrltr
5
Mindspeed Technologies™
FEBECtrltr
4
PthCtrltr
3
FerrCtrltr
2
PdgrCtrltr
1
CX28365/6/4 Data Sheet
ParCtrltr
0
500028C