cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 106

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.5.3.2
2.5.3.3
2-68
TxNEGO output pin is forced to 0. Therefore, TxNEGO does not reflect RxNEGI in
unipolar mode.
Remote Line Loopback
The remote line loopback loops receive data after B3ZS/HDB3 decoding and before
frame recovery back to the line. The decoder output is connected to transmitter B3ZS/
HDB3 encoder input. The remote line loopback provides some LCV error correction
due to the path through the decoder and the encoder. Activation of this loopback does
not affect the receiver data path. The received data is still present on RxDATO pin (it
can be replaced by an all-1s or AIS stream by programming the RxAll1 or RxAIS bits
in the Feature5 Control register). Error insertion on the looped frame is not valid.
The entire transmitter circuit works with the receiver clock (RxCKI). System interface
clock outputs (TxGCKO and TEXTCKO) cannot be related to TxCKI in this mode
and are inactive. TxSYNC is also inactive.
Overwriting the looped frame by an AIS pattern and transmission of AIS to the line is
enabled by programming TxAlm bits in the Mode Control register. However, the
generated pattern is not aligned to the looped frame boundaries and is initiated and
terminated once TxAlm bits change. Idle pattern and RAI transmission due to TxAlm
bits are not enabled during this loopback.
When TxLos bit in Feature2 Control register is set, an all-0s signal is output to the
transmitter and overrides the content of the frame looped from the receiver.
This loopback is activated by setting RlineLp bit in the Feature3 Control register.
Payload Loopback
The payload loopback loops the received frame from the frame recovery circuit output
through the transmitter frame generation circuit input back to the line. The transmitter
is programmed through the Transmit Overhead Insertion1&2 registers to an internal
generation of the Overhead bits, i.e., nothing is inserted via TxDATI or TEXTI pins.
The only exception is that justification control and Stuff Opportunity bits should be
selected to be driven with the data stream, enabling the transmitter to receive them
from the receiver with the payload. The entire transmitter circuit works with the
receiver clock (RxCKI). The system interface clock outputs (TxGCKO and
TEXTCKO) cannot be related to TxCKI in this mode and are inactive. The transmitter
circuit gets the frame alignment signal from the receiver with the data that is looped.
TxSYNC is inactive.
The payload loopback provides framing bits and some LCV error correction due to
the path through the decoder, frame recovery, frame generation, and encoder.
Activation of this loopback does not affect the receiver data path. The received data is
present on RxDATO pin (it can be replaced by an all-1s or AIS stream by
programming RxAll1 or RxAIS bits in Feature5 Control register). Error insertion on
the looped frame is valid in this mode. Overwriting the looped frame by an AIS
pattern and transmission of AIS to the line is enabled by programming TxAlm bits in
the Mode Control register. The generated pattern is aligned to the looped frame
boundaries, and initiated and terminated similarly to normal operation (i.e., when not
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
The Shallow Line loopback and Source loopback cannot be operated simultaneously.
CX28365/6/4 Data Sheet
500028C