cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 11
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cx28365
Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28365.pdf
(228 pages)
- Current page: 11 of 228
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Figures
500028C
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 2-18.
Figure 2-19.
Figure 2-20.
Figure 2-21.
Figure 2-22.
Figure 2-23.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
CX28365 Logic Diagram, Framer, and Cell Delineator Enabled . . . . . . . . . . . . . . . . . . . . . . 1-3
CX28365 Logic Diagram, Cell Delineator Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
CX28365 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
CX28366 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
CX28364 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Framer Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Transmitter Line Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Tx System Side External Overhead Insertion (DS3 FEBE-only Example) . . . . . . . . . . . . . . . 2-4
DS3 System Transmit Timing (TxSYNC Indicates Frame Start) . . . . . . . . . . . . . . . . . . . . . 2-5
DS3 System Transmit Timing (TxSync Indicates Overhead Bits) . . . . . . . . . . . . . . . . . . . . 2-6
DS3 System Transmit Timing (TxSync[i] as Input Indicating Frame Start) . . . . . . . . . . . . . 2-6
E3-G.751 System Transmit Timing (TxSYNC Indicates Frame Start) . . . . . . . . . . . . . . . . . 2-7
E3-G.751 System Transmit Timing (TxSYNC Indicates Overhead Bits) . . . . . . . . . . . . . . . . 2-7
E3-G.832 System Transmit Timing (TxSYNC Indicates Frame Start) . . . . . . . . . . . . . . . . . 2-8
E3-G.832 System Transmit Timing (TxSYNC Indicates Overhead Bits) . . . . . . . . . . . . . . . . 2-8
Line Coding Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Receiver Line Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Receiver System Side Outputs [RxGCKO] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Receiver System Side Outputs [REXTCKO] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Receiver System Side Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Cell Delineation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Header Error Check Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Input/Output Ports Application Example (LIU Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Input/Output Ports Application Example (Framer and LIU Control) . . . . . . . . . . . . . . . . . . 2-63
Source Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
Far-End Line Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Loopback Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
TAP Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Input Hysteresis (Schmitt Trigger Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Line Side Receiver Input Data Setup/Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Line Side Transmitter Output Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
System-Side Transmitter Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
System-Side Receiver Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
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