cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 52

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2-14
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
generated internally or supplied on the TEXTI pin to the transmitter circuit. If bit
ExtFEBE/Cj in Transmit Overhead Insertion 1 Control register is set to 1, the REI-
bit is inserted to the transmitter via the TEXTI pin. If bit ExtFEBE/Cj is set to 0,
REI is internally generated automatically. In the internal-automatic mode, the REI-
bit is set by the transmitter as a reaction to an error detected in a received BIP-8
code (in EM field). In this mode, if the received BIP-8 code at the current frame
does not equal the calculated BIP-8 code over the previously received frame, the
transmitter inserts 1 at the REI-bit for one frame at the first opportunity. As long as
no BIP-8 errors are detected at the received frame, the transmitter inserts 0 at the
transmitted REI-bit.
MA PT—(payload type) Bits 3 to 5 of the MA byte are the payload type field. The
3-bit payload type pattern to be transmitted is contained in bits FEBEC/PT[1:3] at
the Feature1 Control register. Writing a new payload type to the register affects the
next transmitted frame.
MA PD/MI—Bits 6 and 7 of the MA byte are the payload- dependent/multiframe
indicator bits. There are two modes of operation for these bits: SSM mode, and the
normal mode. When bit SSMEn in Feature4 (I) Control register is set to 1, SSM
mode is enabled. In this mode, the MA PD/MI bits act as multiframe indicator bits
(MI). They can be supplied by either an external circuit on TEXTI bit input, or
they can be automatically generated internally by setting of bit ExtFEAC/PD
(when set to 0, it is automatically generated; when set to 1, it is supplied through
the TEXTI pin). When multiframe indication bits are supplied automatically, a 2-
bit rollover counter is implemented. The counter is incremented each frame and its
value is transmitted on MI bits (The MI counter is reset to 00 when enabling
automatic generation of MI bit in SSM mode). When bit SSMEn is set to 0, SSM
mode is disabled and the PD/MI bits act as the payload- dependent bits. When
SSM mode is not set, those bits can be either supplied by external circuitry on the
TEXTI pin by setting bit ExtFEAC/PD bit in the Transmit Overhead Insertion 1
register to 1, or the value to be transmitted can be taken from bits MAPD[1:2] in
register Feature4 (I) Control register by setting bits ExtFEAC/PD and SSMEn to 0.
MA TM/SSM—Bit 8 of the MA byte is the timing marker/SSM bit. There are two
modes of operation for these bits: SSM mode, and the normal mode that is
controlled by the settings of bit SSMEn in Feature4 (I) Control register. If bit
SSMEn is set to 1, SSM mode is enabled. Otherwise, SSM mode is disabled. In
both SSM and normal mode, the bits to be transmitted are written to the register.
When SSM mode is disabled, the TM value to be transmitted is taken from bit
SSM[1]/TM in the Feature4 Control register. When SSM mode is enabled, the 4-
bit SSM message to be transmitted is stored in bits SSM[1]/TM, SSM[2:4] in
Feature4 Control register. In this mode, the bit of the SSM message to be
transmitted is selected according to the value of MI transmitted bits (supplied
through the TEXTI pin or automatically generated).
NR (DL)—The network operator byte source is determined by bits DLMod[2],
DLMod[1], and DLMod[0] at the Transmit Overhead Insertion 1 Control register.
It can be supplied externally on TEXTI. It can be transmitted as all-1s (data link
disabled). The framer is also capable of implementing LAPD data link using an
Mindspeed Technologies™
There are eight options for setting NR and GC sources using the DLMod[2:0] bits
setting at the Transmit Overhead Insertion 1 Control register in a E3-G.832 mode of
operation. The framer is capable of implementing one LAPD data link using an
internal FIFO buffer at a time. In E3-G.832 mode a LAPD data link can either be
implemented on GC or NR, but not on both at the same time.
CX28365/6/4 Data Sheet
500028C