cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 137

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.2.5
0x00—SUMINT (Summary Interrupt Indication Status Register)
PLCPInt
TxCellInt
RxCellInt
0x01—ENSUMINT (Summary Interrupt Control Register)
EnPLCPInt
EnTxCellInt
EnRxCellInt
500028C
—
—
7
7
(1)
(1)
Active-high interrupt from PLCP circuit.
When a logical 1 is read, this bit indicates a Transmit Cell Interrupt. This interrupt is a
summary interrupt and signifies that an interrupt indication occurred in the TxCellInt register
(0x2C).
When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a summary
interrupt and signifies that an interrupt indication occurred in the RxCellInt register (0x2D).
Active-high enable of PLCP interrupt.
When written to a logical 1, this bit enables the transmit cell interrupts located in the TxCellInt
register (0x2C). These interrupts can appear on the MINTR* pin (pin E2), provided that
EnPortInt in the ENSUMPORT register (0x0201) and the CDInten in the PORTINT register
(0xE90) are enabled for that port and the EnIntpin in the GLOB register (0xE00) is enabled.
When written to a logical 1, this bit enables the receive cell interrupts located in the RxCellInt
register (0x2D). These interrupts can appear on the MInt* pin (pin B19), provided that
EnPortInt in the ENSUMPORT register (0x00201) and the CDInten in the PORTINT register
(0xE90) are enabled for that port and the EnIntpin in the GLOB register (0xE00) is enabled.
Status and Interrupt Registers
—
—
6
6
These registers contain interrupt enables, interrupt indications, and status
information.
The SUMINT register indicates the Cell Delineator port summary interrupts.
The ENSUMINT register controls which of the interrupts listed in the SUMINT
register (0x00) appear in the SUMPORT register (0xE04 and 0xE05) and on the
MINTR* (pin E2).
Default after reset: 00
NOTE:
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
—
—
5
5
Mindspeed Technologies™
The interrupt bits in the Cell Delineator register group do not latch status unless the
respective interrupts are enabled. The affected registers are SUMINT (offset 0x00),
TXCELLINT (offset 0x2c), and RXCELLINT (offset 0x2D).
(1)
indicated registers. This bit is a pointer to the next interrupt indication register to be
read. This bit is cleared when the interrupt bits in the corresponding interrupt
indication registers are read and automatically cleared.
This bit is a summary indication of any interrupt events that occurred in the
EnPLCPInt
PLCPInt
4
4
—
—
3
3
—
—
2
2
EnTxCellInt
TxCellInt
1
1
EnRxCellInt
RxCellInt
0
0
Registers
3
-
27