cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 96

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.3.5
2.3.6
2-58
UTOPIA Addressing
Handshaking
The UTOPIA address for each port is stored in bits 0–4 of the UTOP2 register
(0x0E). The default for this value is the port number. For example, the UTOP2
register for port 4 (0x10E [with the offset]) defaults to 04 hex. However, the value can
be changed to any value from 00–1E hex by programming the register to
accommodate multiple devices on the same UTOPIA bus. The value 1F hex is
reserved for the null address. The UTOPIA address should be changed only when the
device or port is in the reset state.
UTOPIA bus conflicts can occur if different CX2836x ports are programmed with
the same multi-PHY address. Under these circumstances, a bus conflict may occur if
data is being transferred through these ports at the same time. A bus conflict
generates an error in BusCnflct (bit 2) of the TXCELL register (0x2E). During a data
collision, data will be transmitted according to port priority the lowest port number
has highest priority.
The CX2836x provides both cell- and octet-level handshaking on its UTOPIA
interface (only cell-level is used in Level 2). Octet-level sends and receives four octets
at a time, while cell-level sends and receives a full cell at a time, depending on FIFO
buffer size and availability. In octet-level handshaking, UTxCLAV is an active low,
FIFO full indicator. In cell-level, it is an active high, cell buffer available indicator.
These two options are selectable in the Handshake bit, bit 1, of the MODE register
(0x0202).
UTxCLAV (transmit cell available): The CX2836x implementation of UTxCLAV is
designed to provide a “look ahead” feature to allow the ATM layer to anticipate when
the FIFO buffers are full. The UTOPIA layer polls the port to determine if that port
has room for a cell. In response, the port asserts (logic1) the UTxCLAV line if it has
room and deasserts (0) the line if it does not have room. The threshold is controlled
by bits [1:0] in the UTOP1 register and, UTOP1[TxFill]. For maximum performance
when using a standard ATM layer device, Mindspeed recommends leaving these set
to 0s.
Preliminary Information/Mindspeed Proprietary and Confidential
0 0
0 1
0 1
1 1
The UTxCLAV is asserted if the UTOPIA FIFO buffer can accept at least
one more complete cell
The UTxCLAV line is asserted if the UTOPIA FIFO buffer has room for at
least two more cells.
The UTxCLAV line is asserted if the UTOPIA FIFO buffer has room for at
least three more cells.
The UTxCLAV line is asserted if the UTOPIA FIFO buffer can accept at
least three more cells.
Mindspeed Technologies™
CX28365/6/4 Data Sheet
500028C