cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 108

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.6
2.6.1
2-70
Joint Test Access Group (JTAG) Interface
Instructions
The CX2836x incorporates printed circuit board testability circuits in compliance
with IEEE Standard P1149.1a–1993, IEEE Standard Test Access Port and Boundary–
Scan Architecture, commonly known as JTAG (Joint Test Action Group).
The JTAG includes a Test Access Port (TAP) and several data registers. The TAP
provides a standard interface through which instructions and test data are
communicated, see
for the CX28344 is available from Mindspeed upon request.
The TAP consists of TDI, TCK, TMS, TDO, and TRST* pins. The TRST* control bit
must be manually operated to take the JTAG port in and out of reset.
Figure 2-23. TAP Diagram
In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST
instructions, an IDCODE instruction is supported.
instructions and their codes.
Table 2-15. JTAG Instruction Codes
EXTEST
SAMPLE/PRELOAD
BYPASS
IDCODE
HIGHZ
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
Instruction
Figure
TRST
TMS
TDO
TCK
TDI
2-23. A Boundary Scan Description Language (BSDL) file
JTAG Port
Table 2-15
Code
lists the JTAG
000
001
111
010
100
CX28365/6/4 Data Sheet
500028_003
500028C