cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 114

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
Table 3-2. Cell Delineator Control and Status Registers (3 of 3)
3-4
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
FOOTNOTE:
(1)
(2)
Register
Address
Offset
One-second latching is enabled by setting EnStatLat (bit 7) in the Global Control register (0xE00) to a logic 1.
One-second latching is enabled by setting EnCntrLat (bit 6) in the Global Control register (0xE00) to a logic 1.
RXCELL
IDLECNTL
IDLECNTM
IDLECNTH
LOCDCNT
TXCNTL
TXCNTM
TXCNTH
CORRCNT
RXCNTL
RXCNTM
RXCNTH
UNCCNT
NONCNTL
NONCNTH
Name
—
—
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Type
Preliminary Information/Mindspeed Proprietary and Confidential
—
—
One-second
Mindspeed Technologies™
Latching
—
—
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Receive Cell Status Control Register
Receive idle cell counter (low byte)
Receive idle cell counter (middle byte)
Receive idle cell counter (high byte)
LOCD Event Counter
Transmitted Cell Counter (low byte)
Transmitted Cell Counter (mid byte)
Transmitted Cell Counter (high byte)
Corrected HEC Error Counter
Received Cell Counter (low byte)
Received Cell Counter (mid byte)
Received Cell Counter (high byte)
Uncorrected HEC Error Counter
Nonmatching Cell Counter (low byte)
Nonmatching Cell Counter (high byte)
Reserved, set to a logic 0
Reserved, set to a logic 0
Description
CX28365/6/4 Data Sheet
Page Number
3-31
3-32
3-32
3-32
3-32
3-33
3-33
3-33
3-33
3-34
3-34
3-34
3-34
3-35
3-35
—
—
500028C