cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 18

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Product Description
Figure 1-2. CX28365 Logic Diagram, Cell Delineator Bypassed
1-4
Input Port1/Interrupt Request/
Input Port2/Transmit Sync
Receive Line Clock[11:0]
Receive Negative[11:0]
Receive Positive[11:0]
Transmit Overhead
One Second Input
Transmit Clock In
Reference Clock
Test Mode Select
Transmit Data In
Processor Clock
Test Data Input
Output Enable
Receive Sync
Address Bus
Write Strobe
8KHz Input
Chip select
Test Reset
Test Clock
Reset
Preliminary Information/Mindspeed Proprietary and Confidential
RefCKI
MCS~
MReset~
MOE~
WR~
MCLK
8KHZIn
TxDATI[11:0]
TxCKI[11:0]
TEXTI[11:0]
MAddr[13:0]
RxSync[11:0]
RxPOSI[11:0]
RxNEGI[11:0]
RxCKI [11:0]
InPort1/LIntR/
InPort2/TxSync[11:0]
TRST~
TMS
TCK
TDI
OneSecIn
Framer Transmit, Receive System Interface
Framer Transmit, Receive Line Interface
Mindspeed Technologies™
Programmable Input/Output
Microprocessor Interface
JTAG Interface
OutPort1/LStatOut[11:0]
OutPort2/LCS~[11:0]
REXTCKO[11:0]
TEXTCKO[11:0]
RxGCKO[11:0]
TxGCKO[11:0]
8KREFO[11:0]
TxPOSO[11:0]
TxNEGO[11:0]
RxDATO[11:0]
TxCKO[11:0]
OneSecOut
MData[7:0]
MINTR~
OutDis
TDO
Transmit Positive
Transmit Negative
Transmit Clock Out
Transmit Gap Clock
Transmit Overhead Clock
Receive Data Output
Receive Overhead Clock
Receive Gap Clock
Receive PLCP Frame Ref
Output Port 1/Line Status
Output Port 2/Chip Select
Test Data Output
Processor Data Bus
Interrupt Request
One Second Output
Output Disable
CX28365/6/4 Data Sheet
500028C
500028_013