cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 28

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Product Description
Table 1-3. Hardware Signal Definition, Transmit/Receive Systems Interface (2 of 3)
1-14
TxGCKO[0]
TxGCKO[1]
TxGCKO[2]
TxGCKO[3]
TxGCKO[4]
TxGCKO[5]
TxGCKO[6]
TxGCKO[7]
TxGCKO[8]
TxGCKO[9]
TxGCKO[10]
TxGCKO[11]
RxGCKO[0]
RxGCKO[1]
RxGCKO[2]
RxGCKO[3]
RxGCKO[4]
RxGCKO[5]
RxGCKO[6]
RxGCKO[7]
RxGCKO[8]
RxGCKO[9]
RxGCKO[10]
RxGCKO[11]
REXTCKO[0]
REXTCKO[1]
REXTCKO[2]
REXTCKO[3]
REXTCKO[4]
REXTCKO[5]
REXTCKO[6]
REXTCKO[7]
REXTCKO[8]
REXTCKO[9]
REXTCKO[10]
REXTCKO[11]
RxDATO[0]
RxDATO[1]
RxDATO[2]
RxDATO[3]
RxDATO[4]
RxDATO[5]
RxDATO[6]
RxDATO[7]
RxDATO[8]
RxDATO[9]
RxDATO[10]
RxDATO[11]
Label
Pin
Framer Transmit
Gapped Clock
Framer Receive
Gapped Clock
Framer Receive
Overhead Clock
Output
Framer Receive Serial
Data Output
Signal
Name
Preliminary Information/Mindspeed Proprietary and Confidential
CX28365
AD25
AC22
AD20
AC21
AD21
AD14
AC15
AD23
AD16
AC17
AD22
AD15
AC16
Pin#
AF18
AE19
AF12
AF19
AE13
AF14
AF21
AE15
AF13
AF20
AE14
Mindspeed Technologies™
C11
D14
C15
A17
D11
B10
A11
D10
D13
B12
A13
D12
B11
A12
D5
D8
D7
D6
D9
C7
B9
B3
B5
B4
CX28366
Pin#
C11
D14
C15
A17
D11
B10
A11
D10
D13
B12
A13
D12
B11
A12
D5
D8
D7
D6
D9
B4
C7
B9
—
—
—
—
—
—
B3
—
—
—
—
—
—
B5
—
—
—
—
—
—
—
—
—
—
—
—
CX28364
Pin#
D14
D11
D10
D13
D12
C11
C7
B9
D5
D8
B3
D7
B5
D6
D9
B4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O/Z
O/Z
O/Z
O/Z
I/O
A gapped clock that is derived from the
falling edge of the TxCKI clock. It is
gapped during Opportunity bits which
are not selected to be inserted with
payload on TxDATI. Its polarity is
programmable.
A gapped clock signal output that is
used to indicate RxDATO serial data
output. RxGCKO clock polarity and
behavior are programmable and have
several options.
Used to indicate chosen Opportunity
bits that output on RxDATO. This output
has a clock pulse for each position of
chosen group of Opportunity bits for the
specific DS3/E3 mode. Its polarity is
programmable.
Serial receive data output from framer.
Data is clocked out on the rising edge of
RxGCKO clock.
Definition
CX28365/6/4 Data Sheet
500028C