cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 85

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.2
2.2.1
500028C
ATM Cell Processor
ATM Cell Transmitter
The CX2836x’s ATM cell receiver block is responsible for recovering cell alignment,
performing detection/correction, and descrambling the payload octets. The resulting
ATM cells are then passed to the ATM layer via the UTOPIA interface.
Simultaneously, the ATM transmitter block is receiving data from the ATM layer,
optionally inserting header fields, optionally calculating the HEC, and sending the
cells to the framers. If no data is being received from the ATM layer, the cell processor
generates idle cells based on the data programmed into the associated registers.
Transmitted cells can be directly mapped into the framer payload or framed using the
Physical Layer Convergence Protocol (PLCP) defined by the ATM Forum DS3
Physical Interface Specification: af-phy-0054.000 (1996) for T3 applications and by
ETSI Standard ETS 300 214 for E3 applications. The cell receiver, accordingly, can
recover cell alignment (also called cell delineation) using the HEC octet when direct
mapping is used or can find PLCP frame alignment when that method is used. The
following paragraphs describe direct cell mapping and PLCP framing is described in
Sections 2.2.3
The Cell Processor has all counters needed for capturing ATM error events and
performs payload CRC calculations as required by the AAL formats. It generates cell
status events, cell counts, and error counts.
The ATM cell transmitter controls the generation and formatting of 53-octet ATM
cells sent to the framer (Line) Transmit ports. This block formats an octet stream
containing ATM data cells from the ATM layer device when those cells are available.
All 53 octets of the data cells may be obtained from the external data source and
formatted into the outgoing octet stream.
This block calculates the HEC octet in the outgoing cell from the header field. The
calculated HEC octet can be inserted in place of the incoming data octet by writing
DisHEC (bit 7) in the CGEN register (0x08) to a logical 0. For testing purposes, this
HEC octet can be corrupted by XORing the calculated value with a specific error
pattern input set in the ERRPAT register (0x0B). This HEC error is achieved by
writing ErrHEC (bit 4) in the CGEN register (0x08) to a logical 1. The remaining 48-
octet payload field of the outgoing cell is obtained from the external data source. The
payload can be scrambled.
When there is no data from the ATM layer device, the cell processor inserts idle cells
automatically in the outgoing octet stream. The 4-octet header field for these idle cells
comes from the TXIDL1–4 registers (0x14–17). The HEC octet is calculated and
inserted automatically. The payload field is filled with the octet contained in the
IDLPAY register (0x0A).
In normal operation, the 4-octet header field in the outgoing cell is passed on from the
ATM layer device. Header patterns can be modified in the TXHDR1–4 registers
(0x10–13) and inserted into outgoing cells in place of header bytes received from the
ATM layer. Whether the original header cells or replacement cells are sent is
controlled by bits 0–4 in the HDRFIELD (0x09) register.
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
through 2.2.5.
Functional Description
2
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