cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 181

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x4F—SR15 (Receive FEAC Byte)
RxFEAC[7:0]
0x50—SR16 (Receive FEAC Stack Byte)
RxFEACS[5:0]
RxFEACSV
RxFEACSM
500028C
RxFEACS[5]
RxFEAC[7]
7
7
RxFEACS[4]
RxFEAC[6]
Only one error type is set according to this priority: OVR, Abort, AlignErr, BadFCS (highest
to lowest).
Receive FEAC Channel Message Byte—If the incoming format is DS3-C-Bit Parity, this
register contains the received byte from the bit-oriented Receive FEAC channel. RxFEAC[0] is
the bit received first and RxFEAC[7] is the last bit received from the line. The Receive FEAC
channel is only defined in DS3-C-Bit Parity format. This byte is meaningless in DS3-M13/
M23, and both E3 modes and should be ignored.
Receive FEAC Channel Stack Message Byte—If the incoming format is DS3-C-Bit Parity, this
register contains the FEAC stack received byte from the bit-oriented Receive FEAC channel.
Receive FEAC message reception is described in Far-End Alarm and Control Channel
Reception in
bit received from the line. This byte is meaningless in DS3-M13/M23 and both E3 modes and
should be ignored.
Receive FEAC Channel Stack Message Byte is Valid— Set on if RxFEACS [5:0] hold a valid
FEAC code word. For a detailed description, refer to Far-End Alarm and Control Channel
Reception sections.
Receive FEAC Channel Stack Has More Data—Set on if the current value of RxFEACS[5:0]
is not the last valid code word in the FEAC stack. For a detailed description, refer to Far-End
Alarm and Control Channel Reception sections.
6
6
Value after reset: Undefined
Direction: Read only
Value after enable: Unaffected
Value after reset: Bits 0–1: 0, Bits 2–7: undefined
Direction: Read only
Value after enable: Bits 0–1: 0, Bits 2–7: undefined
Preliminary Information/Mindspeed Proprietary and Confidential
RxFEACS[3]
RxFEAC[5]
Section
5
5
2.1.2. RxFEACS[0] is the first bit received and RxFEACS[5] is the last
Mindspeed Technologies™
RxFEACS[2]
RxFEAC[4]
4
4
RxFEACS[1]
RxFEAC[3]
3
3
RxFEACS[0]
RxFEAC[2]
2
2
RxFEAC[1]
RxFEACSV
1
1
RxFEACSM
RxFEAC[0]
0
0
Registers
3
-
71