cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 73

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
500028C
When the MINTR* pin is active, an appropriate interrupt identification bit is active or
set. Unless otherwise qualified, the interrupt is associated with the identification bit,
and both are cleared when the identification bit is read. The status indication bits often
parallel the interrupts and can be used for applications preferring polling to interrupts.
Once an interrupt occurs the microprocessor should read the SrcChnl1-SrcChnl4
fields of the Source Channel Status register to identify the interrupt originating
channel. Once the channel is identified and read, the Interrupt Source Status register
identifies which sub-block initiated the interrupt. The interrupt identification fields of
the Status Indication register for that sub-block identifies the type of interrupt. All
interrupts are masked on reset. They are unmasked or made active by setting the
appropriate fields in the AlarmStartInterrupt and AlarmEndInterrupt registers.
The following sections describe the various event indicators encountered in DS3/E3.
Bipolar Violation (BPV), Excessive Zeros (EXZ), and Line Code Violation (LCV)
A BPV is defined as the occurrence of a signal of the same polarity as the previous
one in an AMI mode or rail mode pulse sequence. An EXZ is defined as the
occurrence in rail mode of more than two DS3 or three E3 consecutive 0s, regardless
of the length of the zero string.
A LCV is defined as the occurrence of either EXZ or BPV , excluding those that are
part of the zero substitution code in DS3 mode. In E3 mode, the LCV is defined as the
occurrence of two consecutive BPVs of the same polarity.
In rail mode (B3ZS/HDB3), LCV and EXZ events are counted. In AMI mode, BPV
events are used to increment the LCV counter. In unipolar mode, only LCV is valid,
and the LCV (defined as a pulse on RxNEGI/LCVI pin) counter is updated.
Loss of Signal (LOS)
In DS3, LOS is declared when there are no signal pulses of either polarity over a
period of 100 contiguous pulse intervals in rail mode. The LOS event is terminated
when the pulse density equals or exceeds 33% over a period of 100 contiguous pulse
intervals. The same is true in AMI mode.
In E3 mode, an LOS is declared when there are no signal pulses of either polarity over
a period of 100 contiguous pulse intervals in rail mode. The LOS event is terminated
when the pulse density equals or exceeds 25% over a period of 100 contiguous pulse
intervals. The same definition is true in AMI mode. In unipolar mode, an LOS event
is undefined.
When a LOS is initiated, it generates a LOSStrt interrupt indication and sets the LOS
status indication bit (the LOSAlm field of the Maintenance Status register). Upon the
termination of the LOS event, the LOS event generates a LOSEnd interrupt indication
and clears the LOS status indication bit.
NOTE:
NOTE:
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In reading 16-bit/24-bit counters, software should read the low byte first and then the
high byte/bytes. The counters do not miss or double count any errors during the
microprocessor reads. At reset all counters are cleared.
The presence of one event indicator does or inhibit the other events from occurring
or inhibit the other data channels (Data Link or FEAC). For example, FBE is still active
in OOF, and internal datalink processing is still active in AIS.
Functional Description
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