cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 81

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
500028C
register is not strictly needed for reading from the FIFO buffer. The first byte read
from the FIFO buffer after the RDL is enabled is a status byte, which indicates the
number of data bytes following it, 0 for (b) blocks, additional information field for a1
and a2 blocks. After this, another status byte is again guaranteed, and so forth. The
next FIFO byte type bit is supplied only for systems that do not want to maintain a
count of data bytes after reading each status byte, and would rather query this bit
before reading every single byte in the FIFO buffer.
Interrupt-Driven Mode
The interrupt-driven FIFO buffer reading mode is enabled by unmasking at least one
of the two functional interrupts related to the RDL (FIFO near-full and message
received). The third interrupt (FIFO overrun) is useful for error condition monitoring.
Once an interrupt occurs, the microprocessor reads the SrcChnl1 to SrcChnl4 fields of
the Source Channel Status register to identify which channel is the interrupt’s
originator. It then reads that channel’s Interrupt Source Status register to identify
which part of the chip raised the interrupt (RDL in this case, namely RxDLItr field). It
then reads the interrupt identification fields of the Status Indication register for this
channel’s RDL (the RxNF, RxMsg, and RxOVR fields of the Receive Data Link
Status register) to identify the type of interrupt.
Before reading a status byte from the FIFO buffer, the RDL Status Indication register
(Receive Data Link Status register) is read, the first time after an interrupt to identify
the interrupt’s source, every other time to make sure there are data blocks in the FIFO
buffer still left to read.
Beyond this, options of handling the interrupt are numerous, but one would expect the
microprocessor to read one or more data blocks and/or one or more bytes from the
FIFO buffer. What follows is a possible routine:
Polling Mode
Polling mode is effective when both RDL functional interrupts have been masked.
Polling mode differs from interrupt-driven mode only in that the entry into the service
routine is timer-dependent rather than interrupt-driven. The rest of the handling is
similar to interrupt-driven mode.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
The E3-G.832 framer in question has all its RDL interrupts set to active, with the
near-full threshold set to 32 bytes.
After identifying the source and type of interrupt, if the interrupt type is
Message received: If the microprocessor is busy, do nothing but return; if it is
not busy, read one entire block from the FIFO buffer, then check if the data-
block-in-FIFO indication is set; if not, return, otherwise repeat
FIFO near-full: Read one entire block from the FIFO buffer, check if the data-
block-in-FIFO indication is set; if not, return, otherwise repeat
FIFO overrun: Inform the network management that the system was unable to
cope with the data link throughput, then act as per FIFO near-full.
Mindspeed Technologies™
In this example, from the time a FIFO near-full interrupt occurs until the FIFO buffer
fills up, a minimum period of 12 ms (96 bytes at 8 KB) passes.
Functional Description
2
-
43