cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 88

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.2.3
2-50
PLCP Cell Generation for Transmit
In PLCP formats, the PLCP overhead generation consists of the framing octets A1
and A2, the Path Overhead Identifier (POI) octets, the path overhead (POH) octets,
and the trailer nibbles. The framing, POI, and POH octets are generated by the PLCD
transmit circuitry, but can be selectively disabled if desired. Applicable specifications
regarding DS3 PLCP operation are the BISDN Physical Layer UNI Specification:
ANSI T1.646 (1995) and the ATM Forum DS3 Physical Layer Interface
Specification: af-phy-0054.000 (1996), and TR-TSV-000773.
The A1 and A2 octets are generated with the normal 0xF6/0x28 pattern as the default.
The POI octets are determined by the particular line rate that is selected, but in each
case they consist of a slot count and a parity bit. The DS3 PLCP has 12 slots per
frame, the DS1 and E1 PLCP have 10, and the E3 PLCP has 9. In each case, the POI
octets provide a backwards count of the PLCP slots in the frame, along with a parity
bit. Generation of the A1, A2, POI, B1, and C1 octets can be disabled (written to
0x00) via the Overhead Control [bits 7-4] of PLCPOVH register [addr 0x01]. All path
overhead growth octets Zn are forced to zero. The path user channel F1 is forced to
zero as a default but can be modified using register TXF1 [addr 0x03].
The B1 octet is populated with a BIP-8 code that is calculated over each PLCP frame.
The BIP Error Insert [bit 1] of PLCPOVH controls insertion of BIP-8 errors in the
generated PLCP. If errors are to be inserted, a non-zero value written to the ERRPAT
[addr 0x0B] register inverts the corresponding bits of the B1 octet from that calculated
by the BIP-8 circuit in the following PLCP frame. Insert control bits are cleared after
each frame when the errors are inserted. PLCPOVH can be read to determine if this has
occurred, so the microprocessor can insert BIP-8 errors as desired in each PLCP frame.
This capability can be used to verify far-end FEBE operation. BIP generation can be
disabled via the Overhead Control bits. The fields of the G1 octet (PLCP Path Status)
are controlled by the TXG1 [addr 0x02] register, the AutoFEBE control bit in
PLCPOVH, and the InsFebeErr control bit in PLCPOVH. The FEBE bits occupy the
upper nibble of G1. The FEBE controls operate as shown in
Table 2-8. FEBE Controls
The Yellow Alarm bit in the G1 octet is set to the value contained in TxYellow [bit 3]
in TXG1.
The C1 octet is under control of PhyType[2:0] bits in PMODE [addr 0x04] register,
8kLock[1:0] bits in PLCPSEL [addr 0x00] register, and DisC1 bit in PLCPOVH [addr
0x01] register as shown in
InsFebeErr
Preliminary Information/Mindspeed Proprietary and Confidential
0
0
1
Mindspeed Technologies™
AutoFEBE
1
0
x
Table
2-9.
TxFEBE
a b c d
x x x x
x x x x
According to BIP-8 Errors Received
Upper nibble of ERRPAT
FEBE Field Value
Table
a b c d
2-8.
CX28365/6/4 Data Sheet
500028C