cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 162

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
ExtCP/TR
ExtFEAC/PD
ExtDat
0x2A—CR10 (Transmit Overhead Insertion2 Control Register)
ExtStf
ExtFrmAl
ExtP
ExtRAI
3-52
—
7
DS3-C-Bit Parity mode. In DS3-M13/M23 mode or E3-G.751 mode, Justification Control bits
are inserted via the data stream when this bit is cleared. In E3-G.832 mode, the REI bit is set
automatically by the transmitter upon detection of BIP-8 error if this bit is cleared.
External CP/Trail Trace Control—Set to enable insertion of CP-bits or TR byte via TEXTI pin.
In DS3-C-Bit Parity mode, setting this bit enables insertion of CP field via TEXTI pin. In E3-
G.832 mode, setting this bit enables insertion of Trail Trace byte via TEXTI pin. In E3-G.832,
when this bit is cleared, the transmitter automatically transmits 00(h) on TR byte. In DS3-M13/
M23 and E3-G.751 modes, this bit has no effect.
External FEAC/Payload Dependent/Multiframe Indicator Field Control—Set to enable
insertion of FEAC channel or payload dependent field via TEXTI pin. In DS3-C-Bit Parity
mode, setting this bit enables insertion of FEAC channel via TEXTI pin. In E3-G.832 mode,
setting this bit enables insertion of payload dependent, multiframe indicator field in MA byte
via TEXTI pin. When this bit is cleared, FEAC channel is inserted through a programmable
register (Transmit FEAC Channel Byte) in DS3-C-Bit Parity mode. In E3-G.832, payload
dependent field is inserted through a programmable register (MAPD field in Feature4 control
register) when this bit is cleared and SSMEn bit (in Feature4 Control register) is also cleared.
If SSMEn is set, i.e., bits 6–7 in MA byte are used as a multiframe indicator, the MI is
internally produced cycling through the values 00, 01, 10, and 11 on an arbitrarily defined,
4-frame multiframe. In DS3-M13/M23 and E3-G.751 modes, this bit has no effect.
External Data Control—Set to enable all Opportunity bits to be inserted via the data stream.
When set, this bit overrides the rest of the control bits in this register and in the Transmit
Overhead Insertion2 Control register. It disables internal generation of Opportunity bits
(automatic or through programmable registers) and forces the device to use the Opportunity
bits inserted in the data stream. When clear, overhead configuration is determined by the rest
of the control bits as described above. This bit affects all modes. Setting of TxAlm [1:0] bits is
effective even during ExtDat = 1.
External Stuff Bits—Set to enable insertion of Stuff Opportunity bits via TEXTI pin in DS3-
M13/M23 and E3-G.751 modes. When clear, stuff bits are inserted with the payload. This bit
has no affect in DS3-C-bit parity and E3-G.832 modes.
External Frame Alignment Bits—Set to enable insertion of F and M-bits (DS3 mode), FAS
(E3-G.751), FA1 and FA2 (E3-G.832) bits via TEXTI pin. When clear, the frame alignment
bits are automatically generated by the internal circuitry.
External P-Bit Control—Set to enable insertion of P-bits via TEXTI pin in DS3-C-Bit Parity
and DS3-M13/M23 modes. When clear, P-bits are automatically calculated by the internal
circuitry. In E3-G.751 and E3-G.832 modes, this bit has no effect.
External X/A/RDI-Bit Control—Set to enable insertion of X-bits (in DS3), A-bit (in E3-
G.751), and RDI (in E3-G.832) via TEXTI pin. It affects E3 when AutoRAI bit is clear.
—
6
Default after reset: 00
Direction: Read/Write
Modification: Static
Preliminary Information/Mindspeed Proprietary and Confidential
—
5
Mindspeed Technologies™
—
4
ExtStf
3
ExtFrmAl
2
ExtP
1
CX28365/6/4 Data Sheet
ExtRAI
0
500028C