cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 122

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x05—IOMODE (Input/Output Mode Control Register)
LRxMRKPol
RxCKIPol
LTxMRKPol
TxCKIPol
CsPol
3-12
—
7
LRxMRKPol
This bit determines the Receiver Synchronization Input Polarity. When written to a logical 1,
the active level on the LRxMRK input is high. When written to a logical 0, the active level is
low.
This bit determines the Receiver Clock Input Polarity. When written to a logical 1, the active
edge on the RxCKI input is the falling edge. When written to a logical 0, the active edge is the
rising edge.
This bit determines the Transmitter Synchronization Input Polarity. When written to a logical
1, the active level on the LTxMRK input is high. When written to a logical 0, the active level is
low.
This bit determines the Transmitter Clock Input Polarity. When written to a logical 1, the
active edge on the TxCKI input is the falling edge. When written to a logical 0, the active edge
is the rising edge.
This bit determines the Chip Select Output Polarity. When written to a logical 1, the active
level on the LCs output pin is high. When written to a logical 0, the active level is low.
6
The IOMODE register controls the line interface signal polarities and status outputs.
Default after reset: 00
Modification:
(2)
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
bits 2–4, 6: static
bit 5: dynamic
RxCKIPol
5
Mindspeed Technologies™
For normal operation, the IOMODE register must be set to 0x70. This affects
RxSyncPol, RxClkPol, and TxSyncPol.
LTxMRKPol
4
TxCKIPol
3
CsPol
2
—
1
CX28365/6/4 Data Sheet
—
0
500028C