cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 155

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x25—CR05 (Feature2 Control Register)
TxLOS
TxOvhMrk
TXSYOut
TXSYIn
TxInvClk
LTxCkRis
500028C
—
7
In both modes, FEBEC/PT[1] bit is transmitted first and FEBEC/PT[3] bit is transmitted last.
In both modes, writing a new value to this byte takes effect only starting from the next
transmitted frame. In DS3-M13/M23 and E3-G.751 modes, this field has no effect.
Transmit Loss of Signal—When set, this bit results in the generation of all-0s (LOS) on the
transmit line side. Setting this bit overrides any other programmed or inserted payload and
overhead pattern with 0s.
Transmit Overhead Bits Mark—This bit controls the behavior of TxSync pin when
programmed to be driven as an output. When set, TxSync marks the bit positions of all
Opportunity bits. When cleared, TxSync marks the beginning of a new frame.
TxSync Pin Output Control—When set, the TxSync pin is an output. The transmitter circuit
generates its own frame synchronization mechanism and signals the frame start or the
Opportunity bit positions (according to TxOvhMrk bit) on TxSync pin to the system. When
cleared, TxSync can be an input or undefined according to the value of TXSYIn bit in this
register.
TxSync Pin Input Control—When set, the TxSync pin is an input. The system generates a
synchronization pulse and the transmitter circuit acts according to it. When cleared, TxSync
can be an output or undefined according to the value of TXSYOut bit in this register.
Transmit System Side Inverted Clocks—This bit controls the polarity of TXGAPCK and
TEXTCK output clocks. When the bit is cleared, TXGAPCK and TEXTCK rising edges are
derived from TxCKI falling edge. In this mode, both clock gaps are active-low. When this bit is
set, TXGAPCK and TEXTCK are inverted, TXGAPCK and TEXTCK falling edges are
derived from TxCKI falling edge. In this mode, both clock gaps are active-high.
LIU Transmit Clock Polarity Control—Used to define the TxCKO edge upon which the
transmitter output data on TxPOSO and TxNEGO pins are sampled by the LIU. When set, the
data are clocked out by the chip on the falling edge of TxCKO. It is sampled by the LIU on the
rising edge of TxCKO. When cleared, the data are clocked out by the chip on the rising edge of
TxCKO. It is sampled by the LIU on the falling edge of TxCKO.
—
6
Default after rest: 01
Direction: Read/Write
Modification: Bit 5: dynamic, bits 0–4: static
NOTE:
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
TxLOS
5
Mindspeed Technologies™
TXSYOut and TXSYIn bits must not be set at the same time.
TXSYOut and TXSYIn bits must not be set at the same time.
TxOvhMrk
4
TXSYOut
3
TXSYIn
2
TxInvClk
1
LtxCkRis
0
Registers
3
-
45