cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 75

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
500028C
Alarm Indication Signal (AIS)
In DS3, AIS event is declared when the receiver recognizes the AIS pattern (i.e.,
payload set to a 1010... sequence, with C-bits set to 0, X-bits set to 1, and F-, M-, and
P-bits all valid) for two consecutive frames with ten or less deviations per frame and
when OOF is off. The AIS event is terminated, if in the receive data stream, there are
eleven or more deviations per frame for two consecutive frames or OOF is on.
An E3-G.751 AIS event is declared when four or fewer 0s are received by the receiver
per frame period for two consecutive frame periods regardless of OOF. If OOF is off,
no more than two 0s can be present in the FAS bits in order to differentiate framed and
unframed all 1s. The AIS event is terminated if the receiver sees five or more 0s for
two consecutive frame periods.
In E3-G.832, AIS event is declared when nine or fewer 0s are received per frame
period, for two consecutive frame periods regardless of OOF. If OOF is off no more
than two 0s can be present in the FA bytes in order to differentiate framed and
unframed all 1s. The AIS event is terminated if the receiver sees ten or more 0s per
frame period for two consecutive frames.
The AIS event generates an AISStrt interrupt indication and sets the AIS status
indication bit (AISDet) in the Maintenance Status register. When the AIS event
terminates, AISEnd interrupt indication is generated, and the AIS status indication bit
is cleared.
In the presence of AIS event, (in both DS3 and E3) an all-1s sequence is transmitted
on the RxDATO pin if the RxAutoAll1 filed in the Feature5 Control register is set.
Idle Signal (IDLE)
In DS3, an IDLE event is declared when the receiver recognizes the IDLE pattern
(i.e., payload set to a 11001100... sequence, with Cb3 bits set to 0, X-bits set to 1, and
F-, M- and P-bits all valid) for two consecutive frames with ten or fewer deviations per
frame when OOF is off. The IDLE event is terminated if the receiver has eleven or
more deviations from the expected IDLE pattern per frame for two consecutive frames
or OOF is on.
The IDLE event generates an Idlestrt interrupt indication and sets the IDLE status
indication bit in the Maintenance Status register. When the IDLE event terminates,
IdleEnd interrupt indication is generated and the IDLE status indication bit is cleared.
In the presence of an IDLE event (only in DS3), an all-1s sequence is transmitted on
the RxDATO pin if the RxAutoAll1 field in the Feature5 Control register is set.
Parity Error (PER) and P-Bit Disagreement (PBD)
In DS3, as per ANSI T1.231-1997, the PER event is declared when at least one of the
two P-bits differs in value from the expected value as calculated from the previous
frame. The PBD event is declared when the receive data has two p-bits which are not
equal.
Similarly, in the E3-G.832, the PER event is declared if, in the receive data, at least
one of the eight EM bits differs from the expected value calculated on the previous
frame and OOF is off. PBD is not defined in E3-G.832. Both PER and PBD are
undefined in E3-G.751. The PER event increments the PER counter and the PBD
event increments the PBD counter.
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Mindspeed Technologies™
Functional Description
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