cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 206

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Specifications
4.4.2.1
4-10
Additional Restrictions
The following restrictions apply:
Preliminary Information/Mindspeed Proprietary and Confidential
When the clock source has been changed due to a setup change (RxFIFEn,
LineLp, SourceLp, PayldLp, RlineLp), the CX28365 should not be accessed for
20 of the slowest clock cycles.
After software reset, the CX28365 should not be accessed for 40 of the slowest
clock cycles.
The OneSec pulse minimal width should be 120 ns.
When output pin MINTR* is activated, the microprocessor reads the Source
Channel Status register and must wait at least one-half cycle of the slowest clock to
read the updated information in the Source Channel register.
Mindspeed Technologies™
CX28365/6/4 Data Sheet
500028C