cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 126

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x14—TXIDL1 (Transmit Idle Cell Header Control Register 1)
TxIdl1[7:4]
TxIdl1[3:0]
0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2)
TxIdl2[7:4]
TxIdl2[3:0]
0x16—TXIDL3 (Transmit Idle Cell Header Control Register 3)
TxIdl3[7:0]
3-16
TxIdl1[7]
TxIdl2[7]
TxIdl3[7]
7
7
7
TxIdl1[6]
TxIdl2[6]
TxIdl3[6]
GFC/VPI bits (for UNI they are GFC bits, for NNI the are VPI bits)
VPI bits
VPI bits
VCI bits
VCI bits
6
6
6
The TXIDL1 register contains the first byte of the Transmit Idle Cell Header. It
controls the header value that is inserted in the transmitted idle cells. This header
consists of 32 bits divided among four registers. These bits hold the Transmit Idle Cell
Header values for Octet 1 of the outgoing cell.
Default after reset: 00
The TXIDL2 register contains the second byte of the Transmit Idle Cell Header (see
0x14—TXIDL1). These bits hold the Transmit Idle Cell Header values for Octet 2 of
the outgoing cell.
Default after reset: 00
The TXIDL3 register contains the third byte of the Transmit Idle Cell Header (see
0x14—TXIDL1). These bits hold the Transmit Idle Cell Header values for Octet 3 of
the outgoing cell.
Default after reset: 00
Preliminary Information/Mindspeed Proprietary and Confidential
TxIdl1[5]
TxIdl2[5]
TxIdl3[5]
5
5
5
Mindspeed Technologies™
TxIdl1[4]
TxIdl2[4]
TxIdl3[4]
4
4
4
TxIdl1[3]
TxIdl2[3]
TxIdl3[3]
3
3
3
TxIdl1[2]
TxIdl2[2]
TxIdl3[2]
2
2
2
TxIdl1[1]
TxIdl2[1]
TxIdl3[1]
1
1
1
CX28365/6/4 Data Sheet
TxIdl1[0]
TxIdl2[0]
TxIdl3[0]
0
0
0
500028C