cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 133

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x23—RXIDL4 (Receive Idle Cell Header Control Register 4)
RxIdl4[7:0]
0x24—IDLMSK1 (Receive Idle Cell Mask Control Register 1)
IdlMsk1[7:0]
0x25—IDLMSK2 (Receive Idle Cell Mask Control Register 2)
IdlMsk2[7:0]
500028C
IdlMsk1[7]
IdlMsk2[7]
RxIdl4[7]
7
7
7
IdlMsk1[6]
IdlMsk2[6]
RxIdl4[6]
These bits hold the Receive Idle cell header for Octet 4 of the incoming cell.
These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell.
These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell.
6
6
6
The RXIDL4 register contains the fourth byte of the Receive Idle Cell Header (see
0x20—RXIDL1).
Default after reset: 01
The IDLMSK1 register contains the first byte of the Receive Idle Cell Mask. It
modifies ATM cell screening, which compares the Receive Idle Cell Header Registers
to the incoming cells. Setting a bit in the Mask Register causes the corresponding bit
in the received ATM idle cell header to be disregarded for screening. For example,
setting IDLMSK1 bit 0 to 1 causes cells to be accepted as ATM idle cells with either
1 or 0 in Octet 1, bit 0 position. This header consists of 32 bits divided among four
registers.
Default after reset: 00
The IDLMSK2 register contains the second byte of the Receive Idle Cell Mask (see
0x24—RXMSKL1).
Default after reset: 00
Preliminary Information/Mindspeed Proprietary and Confidential
IdlMsk1[5]
IdlMsk2[5]
RxIdl4[5]
5
5
5
Mindspeed Technologies™
IdlMsk1[4]
IdlMsk2[4]
RxIdl4[4]
4
4
4
IdlMsk1[3]
IdlMsk2[3]
RxIdl4[3]
3
3
3
IdlMsk1[2]
IdlMsk2[2]
RxIdl4[2]
2
2
2
IdlMsk1[1]
IdlMsk2[1]
RxIdl4[1]
1
1
1
IdlMsk1[0]
IdlMsk2[0]
RxIdl4[0]
0
0
0
Registers
3
-
23