cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 80

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2-42
(the byte whose writing leads to this event is referred to as the threshold byte). This
results in an interrupt with the indication FIFO near-full. A type a2 block is marked in
the block type field, block length is set to the number of data octets stored, and a new
block is started on the byte following the last data byte stored.
If the first octet to arrive after the threshold byte is a flag sequence (i.e., the threshold
byte was the last byte of the FCS), the new block is a type a1 block with a length of 0
or a type b block. If the first octet to arrive after the threshold byte is an abort
sequence, the new block is a type b block. Otherwise, the new block contains the
upcoming bytes of the same message.
If the last octet to arrive before the threshold byte is a flag or abort sequence (i.e., the
threshold byte is the status byte of an upcoming message), the type a2 block has a
length of 0, and the new block contains the actual data of the new message; i.e., the
system receives a message received interrupt (on the byte before the threshold byte)
and, shortly afterwards, a Near-Full FIFO interrupt (on the threshold byte).
FIFO Overrun
If the FIFO buffer is full when another byte must be written to it, and the FIFO
overrun interrupt is off, an overrun error occurs, resulting in an interrupt with the
indication FIFO overrun. If the new byte is a data byte, it is lost (i.e., data bytes
already present in the FIFO buffer are not overwritten), and the data block is
immediately terminated and marked as a b block. If the new byte is a status byte, its
writing to the FIFO buffer is postponed until at least one byte has been read from the
FIFO buffer, and it is guaranteed to be a type b status byte.
While the RDL is in overrun state (i.e., until the indication is turned off), all incoming
data bytes are discarded and nothing is written to the FIFO buffer except the status
byte of the message where the overrun error occurred. New data is written to the FIFO
buffer only upon detection of a transition from flag sequence to zero-stuffed data
following the clearing of the interrupt.
Reading Messages from the FIFO
The system reads the contents of the FIFO buffer by accessing the Receive Data Link
Message Byte Status register; each access returns the next byte from the FIFO buffer.
The Receive Data Link(i) Status register is read before a new status is read. This is
done to make sure there are data blocks in the FIFO buffer (RxBlk) and that the type
of the next status byte a1, a2, or type b are fetched from RxGoodBlk.
The FIFO buffer contains zero or more complete data blocks at any time, plus zero or
more bytes of the current incomplete block.
At no time are the bytes of the current incomplete block accessible by the system.
After reading the Receive Data Link(i) Status register, the status itself is read and
understood according to the RxGoodBlk field value.
The data block in the FIFO status indication bit (the RxBlk field in the Receive Data
Link Status register) is cleared if there are 0 complete blocks, otherwise it is set.
Attempting to read the FIFO buffer when this bit is not set returns an undefined value,
but the FIFO read pointer is not incremented.
Although there is a bit in the Status Indication register (Receive Data Link Status
register), that can be queried to inform the system if the next byte to be read from the
FIFO buffer is a status or a data byte (StatByte field), the bit in the Status Indication
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CX28365/6/4 Data Sheet
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