cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 86

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.2.1.1
2.2.2
2.2.2.1
2-48
ATM Cell Receiver
HEC Generation
In normal operation, the cell processor calculates the HEC for the four header bytes of
each cell coming from the ATM layer. It then adds the HEC coset (55 hex, by ATM
standards) and inserts the result in octet 5 of the outgoing cell. HEC calculation can be
disabled by setting bit 7 of CGEN (0x08) to 1. When HEC is disabled, the cell
processor leaves the contents of the HEC field unchanged and transmits whatever data
is placed in that field by the ATM layer.
The HEC coset is used to maintain a value other than 0 in the HEC field. If the first four
bytes in the header are 0, the HEC derived from these bytes is also 0. When this occurs
and there are strings of 0s in the data, the receiver cannot determine cell boundaries.
Therefore, it is recommended that the value 55 hex be added to the HEC before
transmission. To enable the HEC coset on the transmit side, set bit 6 in register CGEN
(0x08) to 1. To enable the receive HEC coset, set bit 5 in register CVAL (0x0C) to 1.
The ATM cell receiver performs cell delineation on incoming data cells by searching
for the position of a valid HEC field within the cell. The HEC coset can be either
active or inactive; this is determined in bit 5 in the CVAL (0x0C) register.
HEC Based Cell Delineation
The ATM block receives octets from the framers and recovers ATM cells by means of
cell delineation. Cell delineation is achieved by aligning ATM cell boundaries using
the HEC algorithm. Four consecutive bytes are chosen and the HEC value is
calculated. The result is compared with the value of the following byte. This hunt is
continued by shifting this four-byte window, one byte at a time, until the calculated
HEC value equals the received HEC value. When this occurs, a pre-sync state is
declared and the next 48 bytes are assumed to be payload. The ATM block calculates
HEC on the four bytes following this payload, assuming that a new cell has begun. If
seven consecutive header blocks are found, synchronization is declared. If any HEC
calculation fails in the pre-sync state, the process begins again (see
Synchronization is held until seven consecutive incorrect HECs are received. At this
time, the hunt state is reinitiated.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
The cell delineator can receive cells when the receive framer indicates OOF. Although
the cells are good unless the CD reports the contrary, the cells must be considered
suspect. The CD must be disabled when in the OOF state. This is accomplished by
asserting the port logic reset, bit 9, in the PORTn Mode Control registers at offsets
0xE80Q–0xE8B of the Common register group.
CX28365/6/4 Data Sheet
Figure
2-16).
500028C