cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 157

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x27—CR07 (Feature4 Control Register)
SSMEn
SSM[1]/TM
SSM[2:4]
MAPD[1:2]
500028C
—
7
SSM Mode Enable—Set to enable usage of bit 8 in the MA byte as an SSM field and of bits 6–
7 in the MA byte as a multiframe indicator (MI) field. When cleared, bit 8 in the MA byte is
the timing marker (TM) field and bits 6–7 in the MA byte are used as payload dependent (PD)
field.
SSM MSB/Timing Marker Bit Field—When SSM mode is enabled (SSMEn bit is set), this bit
is the MS bit (transmitted first) to be sent in the SSM field (bit 8 in MA byte). When MI field
has a value of 00, SSM [1] is inserted in the frame. When SSM mode is disabled (SSMEn bit is
cleared), this bit is the timing marker. It is inserted on every frame in bit 8 position in the MA
byte.
SSM Bit Field—When SSM mode is enabled (SSMEn bit is set), set to the three LS bits
pattern to be sent in the SSM field (bit 8 of MA byte) according to the multiframe phase
indicated by MI field. When MI field has a value of 01, SSM [2] is inserted in the frame.
When MI field has a value of 10, SSM [3] is inserted in the frame. When MI field has a value
of 11, SSM [4] is inserted in the frame. When SSM mode is disabled, this field is ignored.
Payload Dependent Field in MA byte—When SSM mode is disabled (SSMEn bit in this
register is cleared) and ExtFEAC/PD bit in Transmit Overhead Insertion register 1 is cleared,
this field is sent in every frame in bits 6–7 of the MA byte. MAPD [1] bit transmits first. If
SSM mode is enabled or ExtFEAC/PD is set, this field is ignored.
SSMEn
6
Default after reset: 00
Direction: Read/Write
Modification: Bits 0–5: dynamic, bit 6: static
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
SSM[1]/TM
5
Mindspeed Technologies™
This control register has an effect only in E3-G.832 mode. In DS3 and E3-G.751
modes the content of this register is ignored.
SSM[2]
4
SSM[3]
3
SSM[4]
2
MAPD[1]
1
MAPD[2]
0
Registers
3
-
47