cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 64

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
Table 2-4. Setting the Error Insertion1 Control Register in DS3 Mode
2-26
Framing F
Framing M
P-bit parity
P-bit parity
disagreement
CP bit error
(path parity)
RAI
X-bit
disagreement
FEBE
FOOTNOTE:
(1)
(2)
In DS3 C-bit parity mode.
Active in C-bit parity only.
(2)
Error
(1)
FrmErrF
FrmErrM
YelErr
ParErr
ParDgrErr
CPErr
XdgrErr
FEBEErr
Bit
insertion of one requested error at the next valid opportunity for each error. Once the
error is inserted, the relevant control bit is automatically cleared. Several different
error insertions can be set at the same time by setting more than one error control bit;
each error selection is cleared when the appropriate error is inserted. Before setting
the control bits for another error insertion, they must be polled for the desired errors
and the relevant control bits, must be checked for zero. Writing zero to the control bits
does not affect their settings.
The errors that can be inserted, and their effect on the transmitted data, are specified
for each basic mode of operation.
DS3 Mode
In DS3 mode (both in M13/M23 and in C-bit parity mode), errors listed in
can be transmitted by setting bits at the Error Insertion1 Control register.
Preliminary Information/Mindspeed Proprietary and Confidential
Set To
Mindspeed Technologies™
1
1
1
1
1
1
1
1
A single F-bit error is inserted by inverting the next transmitted F-bit
(only one bit).
A single M-bit error is inserted by inverting the next transmitted M-bit
(one M-bit).
Transmission of incorrect value in the two P-bits (i.e., incorrect parity
calculation over the previous frame). In this case, the next two P-bits of a
single frame to be transmitted are inverted.
Transmission of unequal P-bits at the next opportunity (performed by
inverting the next transmitted P-bit).
Transmission of an incorrect value in the three CP bits in an M-frame. It
is performed by inverting the three CP bits of a single M-frame at the
next opportunity.
Transmission of the opposite value of the M-frame X-bits than the
expected or set value. This is performed by inverting the two X-bits
transmitted in a single M-frame at the next opportunity. Thus, if RAI is
set to be transmitted, the X-bits are set to 1 (instead of 0). If RAI alarm is
not set to be transmitted, both X-bits are transmitted as 0 (instead of 1).
Transmission of opposite values of both X-bits in an M-frame. The
setting of XdgrErr to 1 causes the two X-bits of a single M to be
transmitted with opposite values by inverting the next X-bit to be
transmitted.
Transmission of opposite of the expected code in FEBE bits (the three C-
bits in Subframe 4). When FEBE bits are set to be internally-automatically
generated, setting a FEBE error insertion results in transmission of a 111
code (no error code) in FEBE bits of a single M-frame (at the next
opportunity) if a frame error or a C-bit parity error is detected. Otherwise,
it transmits the value stored in FEBEC/PT[1:3] in the Feature1 Control
register.
Description
CX28365/6/4 Data Sheet
Table 2-4
500028C