cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 105
cx28365
Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28365.pdf
(228 pages)
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CX28365/6/4 Data Sheet
2.5.3
Figure 2-22. Loopback Types
2.5.3.1
500028C
Loopback
Source
Framer Loopbacks
The framer provides a complete set of loopbacks for diagnostics, maintenance, and
troubleshooting of each channel. All loopbacks perform clock and data switching, if
necessary. The activation and deactivation of a specific loopback are done through
programmable control bits. Because activation and deactivation of a loopback causes
internal circuits to switch between clocks, after writing to a loopback control bit, the
microprocessor should not access any of the device registers (read or write) for the 20
slowest clock cycles.
Shallow Line Loopback
The Shallow Line loopback loops the receiver inputs before B3ZS/HDB3 decoding
back to the line through the transmitter outputs. The Shallow Line loopback provides
LCV transparency, i.e., LCVs are transmitted exactly as received. The receiver data
path is not affected by activation of this loopback, and the received data is still present
on the RxDATO pin (it can be replaced by an all-1s or AIS stream by programming
RxAll1 or RxAIS bits in the Feature5 Control register).
The entire transmitter circuit works with the receiver clock (RXCKI); therefore, the
system interface clock outputs (TxGCKO and TEXTCKO) cannot be related to
TxCKI in this mode and are inactive. TxSYNC is also inactive. Error insertion on the
looped framer is not valid.
When the TxLOS bit in Feature2 Control register is set, an all-0s signal is output on
the transmitter and overrides the content of the frame looped from the receiver.
This loopback is activated by setting LineLp bit in the Mode Control register.
When the receiver and the transmitter are programmed to be in shallow line loopback,
and the line code is set to unipolar (NRZMod bit in Feature Control register is set), the
Decoder
Encoder
Shallow
Line
Loop
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
Remote Line
Loopback
Transmitter
Receiver
Loopback
Payload
Functional Description
500028_039
2
-
67
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