R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 121
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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Bit
6 to 4
3
2 to 0
Bit Name
IFC[2:0]
RNGS
PFC[2:0]
Initial
Value
000
0
011
R/W
R/W
R/W
R/W
Description
Internal Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
Output Range Select for PLL Circuit 1
When the multiplication ratio for the PLL circuit 1 is
specified to × 3, set this bit according to the output
frequency of the PLL circuit 1.
0: Low frequency mode
1: High frequency mode
Peripheral Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
(Output frequency of the PLL circuit 1 is equal to
or smaller than 120 MHz.)
(Multiplication ratio for the PLL circuit 1 is specified
to × 3 and its output frequency exceeds 120 MHz.)
Rev. 2.00 Sep. 07, 2007 Page 89 of 1312
Section 4 Clock Pulse Generator (CPG)
REJ09B0320-0200
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