R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 751

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 16.10 shows a sample flowchart for initializing the SCIF.
Set TE and RE bits in SCSCR to 1,
PFC setting for external pins used
Set RTRG[1:0] and TTRG[1:0] bits
in SCSCR (leaving TE, RE, TIE,
and set TIE, RIE, and REIE bits
Set TFRST and RFRST bits
in SCFCR, and clear TFRST
and BRK flags in SCFSR,
Figure 16.10 Sample Flowchart for SCIF Initialization
and RIE bits cleared to 0)
Set data transfer format
in SCFCR to 1 to clear
After reading ER, DR,
Clear TE and RE bits
write 0 to clear them
Set value in SCBRR
Start of initialization
and RFRST bits to 0
Set CKE[1:0] bits
End of initialization
SCK, TxD, RxD
the FIFO buffer
in SCSCR to 0
in SCSMR
Section 16 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Leave the TE and RE bits cleared
to 0 until the initialization almost
ends.
Set the data transfer format in
SCSMR.
Set the CKE1 and CKE0 bits.
Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used.
Sets PFC for external pins used.
Set as RxD input at reciving and
TxD at transmission.
Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the TxD,
RxD, and SCK pins to be used.
When transmitting, the TxD pin
will go to the mark state.
When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCK pin at this
point.
Rev. 2.00 Sep. 07, 2007 Page 719 of 1312
REJ09B0320-0200