R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 13

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4
7.5
Section 8 Cache .................................................................................................187
8.1
8.2
8.3
8.4
Section 9 Bus State Controller (BSC)................................................................205
9.1
9.2
9.3
9.4
7.3.4
7.3.5
7.3.6
Operation ........................................................................................................................... 177
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Usage Notes ....................................................................................................................... 184
Features.............................................................................................................................. 187
8.1.1
Register Descriptions ......................................................................................................... 190
8.2.1
8.2.2
Operation ........................................................................................................................... 195
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory-Mapped Cache .................................................................................................... 200
8.4.1
8.4.2
8.4.3
8.4.4
Features.............................................................................................................................. 205
Input/Output Pins ............................................................................................................... 207
Area Overview ................................................................................................................... 209
9.3.1
9.3.2
Register Descriptions ......................................................................................................... 211
9.4.1
9.4.2
9.4.3
Break Data Mask Register (BDMR)..................................................................... 171
Break Bus Cycle Register (BBR).......................................................................... 172
Break Control Register (BRCR) ........................................................................... 174
Flow of the User Break Operation ........................................................................ 177
Break on Instruction Fetch Cycle.......................................................................... 178
Break on Data Access Cycle................................................................................. 179
Value of Saved Program Counter ......................................................................... 180
Usage Examples.................................................................................................... 181
Cache Structure..................................................................................................... 187
Cache Control Register 1 (CCR1) ........................................................................ 190
Cache Control Register 2 (CCR2) ........................................................................ 192
Searching Cache ................................................................................................... 195
Read Access.......................................................................................................... 197
Prefetch Operation (Only for Operand Cache) ..................................................... 197
Write Operation (Only for Operand Cache).......................................................... 197
Write-Back Buffer (Only for Operand Cache)...................................................... 198
Coherency of Cache and External Memory .......................................................... 200
Address Array ....................................................................................................... 200
Data Array ............................................................................................................ 201
Usage Examples.................................................................................................... 203
Notes ..................................................................................................................... 204
Address Map ......................................................................................................... 209
Data Bus Width and Pin Function Setting for Individual Areas ........................... 210
CSn Control Register (CSnCNT) (n = 0 to 6)....................................................... 213
CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ............................. 215
SDRAMCm Control Register (SDCmCNT) (m = 0, 1)........................................ 217
Rev. 2.00 Sep. 07, 2007 Page xiii of xxxii