R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 644
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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Section 13 8-Bit Timers (TMR)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.
Rev. 2.00 Sep. 07, 2007 Page 612 of 1312
REJ09B0320-0200
Bit
4
3, 2
1, 0
2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first
Bit Name
OS[3:2]
OS[1:0]
compare match occurs after resetting.
Initial
Value
0
00
00
R/W
R
R/W
R/W
Description
Reserved
This is a read-only bit and cannot be modified.
Output Select 3 and 2*
These bits select a method of TMO pin output when
compare match B of TCORB and TCNT occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B occurs
Output Select 1 and 0*
These bits select a method of TMO pin output when
compare match A of TCORA and TCNT occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A occurs
(toggle output)
(toggle output)
2
2
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