R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 987

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R5S72611

Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Note: The setting of this register is reapplied on each sector-to-sector transition.
Bit
4
3
2 to 0
Bit Name
MD_AUTOS1
MD_AUTOS2
MD_SEC[2:0]
Initial
Value
0
0
010
R/W
R/W
R/W
R/W
Description
Criteria for Mode Determination when MD_AUTO = 1
0: Mode determination is done when the sync code is
1: Mode determination is always done
This bit is only valid when MD_AUTO = 1. If the mode
cannot be determined, the mode of the previous sector
is used. When this bit is cleared to 0, mode
determination is only done when the sync code is
detected for the sector.
Criteria for Mode 2 Form Determination when
MD_AUTO = 1
0: The sector is assumed to be non-XA if the two form
1: No determination of XA or non-XA for the sector.
This bit is only valid when MD_AUTO = 1.
Sector Type
000: Setting prohibited
001: Mode 0
010: Mode 1
011: Long (Mode 0, Mode 1, or Mode 2 with no
100: Setting prohibited
101: Mode 2 Form 1
110: Mode 2 Form 2
111: Mode 2 with automatic form detection
If the form cannot be determined when set to B'111, it is
processed as Mode 2 not XA.
detected
code bytes in the subheader do not match
The first form byte is regarded as valid. However,
the two form bytes are compared, and the result is
reflected in a status bit.
EDC/ECC data)
Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 955 of 1312
REJ09B0320-0200

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