R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 205

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

[Legend]
x:
Bit
7, 6
5, 4
3, 2
1, 0
Don't care
Bit Name
CD[1:0]
ID[1:0]
RW[1:0]
SZ[1:0]
Initial
Value
00
00
00
00
R/W
R/W
R/W
R/W
R/W
Operand Size Select
Description
C Bus Cycle/I Bus Cycle Select
Select the C bus cycle or I bus cycle as the bus cycle
of the break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
Instruction Fetch/Data Access Select
Select the instruction fetch cycle or data access cycle
as the bus cycle of the break condition. If the
instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
Read/Write Select
Select the read cycle or write cycle as the bus cycle of
the break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
Select the operand size of the bus cycle for the break
condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
data access cycle
Rev. 2.00 Sep. 07, 2007 Page 173 of 1312
Section 7 User Break Controller (UBC)
REJ09B0320-0200