R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 143

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.7
5.7.1
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal
instructions, and integer division exceptions, as shown in table 5.10.
Table 5.10 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
Floating-point
operation
instruction
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Undefined code anywhere
besides in a delay slot
Division by zero
Negative maximum value ÷ (−1)
Instructions that cause disabled
operation exception defined by
IEEE754 standard or division
exception by zero. Instructions
that could cause overflow,
underflow, or imprecise
exception.
Comment
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
DIVU, DIVS
DIVS
Rev. 2.00 Sep. 07, 2007 Page 111 of 1312
Section 5 Exception Handling
REJ09B0320-0200