R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 879

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

<Longword Read Operation>
The TXPR1 register cannot be modified and it is always fixed to '0'. The TXPR0 controls
Mailbox-15 to Mailbox-1. The CPU may set the TXPR bits to affect any message being
considered for transmission by writing a '1' to the corresponding bit location. Writing a '0' has no
effect, and TXPR cannot be cleared by writing a '0' and must be cleared by setting the
corresponding TXCR bits. TXPR may be read by the CPU to determine which, if any,
transmissions are pending or in progress. In effect there is a transmit pending bit for all Mailboxes
except for the Mailbox-0. Writing a '1' to a bit location when the mailbox is not configured to
transmit is not allowed.
The RCAN-ET will clear a transmit pending flag after successful transmission of its
corresponding message or when a transmission abort is requested successfully from the TXCR.
The TXPR flag is not cleared if the message is not transmitted due to the CAN node losing the
arbitration process or due to errors on the CAN bus, and RCAN-ET automatically tries to transmit
it again unless its DART bit (Disable Automatic Re-Transmission) is set in the Message-Control
of the corresponding Mailbox. In such case (DART set), the transmission is cleared and notified
through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit within the Abort
Acknowledgement Register (ABACK).
If the status of the TXPR changes, the RCAN-ET shall ensure that in the identifier priority scheme
(MCR2 = 0), the highest priority message is always presented for transmission in an intelligent
way even under circumstances such as bus arbitration losses or errors on the CAN bus. Please
refer to section 19.6, Application Note, for details.
Always
H'0000
when TXPR1 (= H'0000) is read.
TXPR1
TXPR0 is stored into Temp,
H'020
16-bit peripheral bus
<Upper word read>
Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
TXPR0
Temp
H'022
Consecutive access
Rev. 2.00 Sep. 07, 2007 Page 847 of 1312
Temp is read instead of TXPR0.
TXPR1
H'020
16-bit peripheral bus
<Lower word read>
TXPR0
Temp
H'022
REJ09B0320-0200